| Message ID | DM4PR11MB5487F66E682E37F118DCEB74EC872@DM4PR11MB5487.namprd11.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
| Series | i386: Fix some vex insns that prohibit egpr | expand |
> -----Original Message----- > From: Kong, Lingling <lingling.kong@intel.com> > Sent: Wednesday, August 14, 2024 9:38 AM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao <hongtao.liu@intel.com>; Jiang, Haochen > <haochen.jiang@intel.com> > Subject: [PATCH] i386: Fix some vex insns that prohibit egpr > > Although these vex insn have evex counterpart, but when it uses the displayed > vex prefix should not support APX EGPR. > Like TARGET_AVXVNNI, TARGET_IFMA and TARGET_AVXNECONVERT. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > gcc/ChangeLog: > > * config/i386/sse.md (vpmadd52<vpmadd52type><mode>): > Prohibit egpr for vex version. > (vcvtneps2bf16_v8sf): Ditto. > (vcvtneps2bf16_v8sf): Ditto. > (vpdpwssds_<mode>): Ditto. > (vpdpwssd_<mode>): Ditto. > (vpdpbusds_<mode>): Ditto. > (vpdpbusd_<mode>): Ditto. > --- > gcc/config/i386/sse.md | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > d1010bc5682..7b9f619e112 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -29886,7 +29886,7 @@ > (unspec:VI8_AVX2 > [(match_operand:VI8_AVX2 1 "register_operand" "0,0") > (match_operand:VI8_AVX2 2 "register_operand" "x,v") > - (match_operand:VI8_AVX2 3 "nonimmediate_operand" "xm,vm")] > + (match_operand:VI8_AVX2 3 "nonimmediate_operand" "xjm,vm")] > VPMADD52))] > "TARGET_AVXIFMA || (TARGET_AVX512IFMA && TARGET_AVX512VL)" > "@ > @@ -30253,7 +30253,7 @@ > (unspec:VI4_AVX2 > [(match_operand:VI4_AVX2 1 "register_operand" "0,0") > (match_operand:VI4_AVX2 2 "register_operand" "x,v") > - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] > + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] > UNSPEC_VPDPBUSD))] > "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" > "@ > @@ -30321,7 +30321,7 @@ > (unspec:VI4_AVX2 > [(match_operand:VI4_AVX2 1 "register_operand" "0,0") > (match_operand:VI4_AVX2 2 "register_operand" "x,v") > - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] > + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] Also need to set attr addr to gpr16 for the alternative. > UNSPEC_VPDPBUSDS))] > "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" > "@ > @@ -30389,7 +30389,7 @@ > (unspec:VI4_AVX2 > [(match_operand:VI4_AVX2 1 "register_operand" "0,0") > (match_operand:VI4_AVX2 2 "register_operand" "x,v") > - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] > + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] > UNSPEC_VPDPWSSD))] > "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" > "@ > @@ -30457,7 +30457,7 @@ > (unspec:VI4_AVX2 > [(match_operand:VI4_AVX2 1 "register_operand" "0,0") > (match_operand:VI4_AVX2 2 "register_operand" "x,v") > - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] > + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] > UNSPEC_VPDPWSSDS))] > "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" > "@ > @@ -30681,7 +30681,7 @@ > [(set (match_operand:V8BF 0 "register_operand" "=x,v") > (vec_concat:V8BF > (float_truncate:V4BF > - (match_operand:V4SF 1 "nonimmediate_operand" "xm,vm")) > + (match_operand:V4SF 1 "nonimmediate_operand" "xjm,vm")) > (match_operand:V4BF 2 "const0_operand")))] > "TARGET_AVXNECONVERT || (TARGET_AVX512BF16 && > TARGET_AVX512VL)" > "@ > @@ -30745,7 +30745,7 @@ > (define_insn "vcvtneps2bf16_v8sf" > [(set (match_operand:V8BF 0 "register_operand" "=x,v") > (float_truncate:V8BF > - (match_operand:V8SF 1 "nonimmediate_operand" "xm,vm")))] > + (match_operand:V8SF 1 "nonimmediate_operand" "xjm,vm")))] > "TARGET_AVXNECONVERT || (TARGET_AVX512BF16 && > TARGET_AVX512VL)" > "@ > %{vex%} vcvtneps2bf16{y}\t{%1, %0|%0, %1} @@ -31216,7 +31216,7 @@ > [(set (match_operand:VF1_128_256 0 "register_operand" "=x") > (vec_duplicate:VF1_128_256 > (float_extend:SF > - (match_operand:BF 1 "memory_operand" "m"))))] > + (match_operand:BF 1 "memory_operand" "jm"))))] > "TARGET_AVXNECONVERT" > "vbcstnebf162ps\t{%1, %0|%0, %1}" > [(set_attr "prefix" "vex") > @@ -31226,7 +31226,7 @@ > [(set (match_operand:VF1_128_256 0 "register_operand" "=x") > (vec_duplicate:VF1_128_256 > (float_extend:SF > - (match_operand:HF 1 "memory_operand" "m"))))] > + (match_operand:HF 1 "memory_operand" "jm"))))] > "TARGET_AVXNECONVERT" > "vbcstnesh2ps\t{%1, %0|%0, %1}" > [(set_attr "prefix" "vex") > @@ -31240,7 +31240,7 @@ > [(set (match_operand:V4SF 0 "register_operand" "=x") > (float_extend:V4SF > (vec_select:<ssehalfvecmode> > - (match_operand:VHFBF_128 1 "memory_operand" "m") > + (match_operand:VHFBF_128 1 "memory_operand" "jm") > (parallel [(const_int 0) (const_int 2) > (const_int 4) (const_int 6)]))))] > "TARGET_AVXNECONVERT" > @@ -31252,7 +31252,7 @@ > [(set (match_operand:V8SF 0 "register_operand" "=x") > (float_extend:V8SF > (vec_select:<ssehalfvecmode> > - (match_operand:VHFBF_256 1 "memory_operand" "m") > + (match_operand:VHFBF_256 1 "memory_operand" "jm") > (parallel [(const_int 0) (const_int 2) > (const_int 4) (const_int 6) > (const_int 8) (const_int 10) > @@ -31266,7 +31266,7 @@ > [(set (match_operand:V4SF 0 "register_operand" "=x") > (float_extend:V4SF > (vec_select:<ssehalfvecmode> > - (match_operand:VHFBF_128 1 "memory_operand" "m") > + (match_operand:VHFBF_128 1 "memory_operand" "jm") > (parallel [(const_int 1) (const_int 3) > (const_int 5) (const_int 7)]))))] > "TARGET_AVXNECONVERT" > @@ -31278,7 +31278,7 @@ > [(set (match_operand:V8SF 0 "register_operand" "=x") > (float_extend:V8SF > (vec_select:<ssehalfvecmode> > - (match_operand:VHFBF_256 1 "memory_operand" "m") > + (match_operand:VHFBF_256 1 "memory_operand" "jm") > (parallel [(const_int 1) (const_int 3) > (const_int 5) (const_int 7) > (const_int 9) (const_int 11) > -- > 2.31.1
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d1010bc5682..7b9f619e112 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -29886,7 +29886,7 @@ (unspec:VI8_AVX2 [(match_operand:VI8_AVX2 1 "register_operand" "0,0") (match_operand:VI8_AVX2 2 "register_operand" "x,v") - (match_operand:VI8_AVX2 3 "nonimmediate_operand" "xm,vm")] + (match_operand:VI8_AVX2 3 "nonimmediate_operand" "xjm,vm")] VPMADD52))] "TARGET_AVXIFMA || (TARGET_AVX512IFMA && TARGET_AVX512VL)" "@ @@ -30253,7 +30253,7 @@ (unspec:VI4_AVX2 [(match_operand:VI4_AVX2 1 "register_operand" "0,0") (match_operand:VI4_AVX2 2 "register_operand" "x,v") - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] UNSPEC_VPDPBUSD))] "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" "@ @@ -30321,7 +30321,7 @@ (unspec:VI4_AVX2 [(match_operand:VI4_AVX2 1 "register_operand" "0,0") (match_operand:VI4_AVX2 2 "register_operand" "x,v") - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] UNSPEC_VPDPBUSDS))] "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" "@ @@ -30389,7 +30389,7 @@ (unspec:VI4_AVX2 [(match_operand:VI4_AVX2 1 "register_operand" "0,0") (match_operand:VI4_AVX2 2 "register_operand" "x,v") - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] UNSPEC_VPDPWSSD))] "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" "@ @@ -30457,7 +30457,7 @@ (unspec:VI4_AVX2 [(match_operand:VI4_AVX2 1 "register_operand" "0,0") (match_operand:VI4_AVX2 2 "register_operand" "x,v") - (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xm,vm")] + (match_operand:VI4_AVX2 3 "nonimmediate_operand" "xjm,vm")] UNSPEC_VPDPWSSDS))] "TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)" "@ @@ -30681,7 +30681,7 @@ [(set (match_operand:V8BF 0 "register_operand" "=x,v") (vec_concat:V8BF (float_truncate:V4BF - (match_operand:V4SF 1 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SF 1 "nonimmediate_operand" "xjm,vm")) (match_operand:V4BF 2 "const0_operand")))] "TARGET_AVXNECONVERT || (TARGET_AVX512BF16 && TARGET_AVX512VL)" "@ @@ -30745,7 +30745,7 @@ (define_insn "vcvtneps2bf16_v8sf" [(set (match_operand:V8BF 0 "register_operand" "=x,v") (float_truncate:V8BF - (match_operand:V8SF 1 "nonimmediate_operand" "xm,vm")))] + (match_operand:V8SF 1 "nonimmediate_operand" "xjm,vm")))] "TARGET_AVXNECONVERT || (TARGET_AVX512BF16 && TARGET_AVX512VL)" "@ %{vex%} vcvtneps2bf16{y}\t{%1, %0|%0, %1} @@ -31216,7 +31216,7 @@
Although these vex insn have evex counterpart, but when it uses the displayed vex prefix should not support APX EGPR. Like TARGET_AVXVNNI, TARGET_IFMA and TARGET_AVXNECONVERT. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: * config/i386/sse.md (vpmadd52<vpmadd52type><mode>): Prohibit egpr for vex version. (vcvtneps2bf16_v8sf): Ditto. (vcvtneps2bf16_v8sf): Ditto. (vpdpwssds_<mode>): Ditto. (vpdpwssd_<mode>): Ditto. (vpdpbusds_<mode>): Ditto. (vpdpbusd_<mode>): Ditto. --- gcc/config/i386/sse.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (vec_duplicate:VF1_128_256 (float_extend:SF - (match_operand:BF 1 "memory_operand" "m"))))] + (match_operand:BF 1 "memory_operand" "jm"))))] "TARGET_AVXNECONVERT" "vbcstnebf162ps\t{%1, %0|%0, %1}" [(set_attr "prefix" "vex") @@ -31226,7 +31226,7 @@ [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (vec_duplicate:VF1_128_256 (float_extend:SF - (match_operand:HF 1 "memory_operand" "m"))))] + (match_operand:HF 1 "memory_operand" "jm"))))] "TARGET_AVXNECONVERT" "vbcstnesh2ps\t{%1, %0|%0, %1}" [(set_attr "prefix" "vex") @@ -31240,7 +31240,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x") (float_extend:V4SF (vec_select:<ssehalfvecmode> - (match_operand:VHFBF_128 1 "memory_operand" "m") + (match_operand:VHFBF_128 1 "memory_operand" "jm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))))] "TARGET_AVXNECONVERT" @@ -31252,7 +31252,7 @@ [(set (match_operand:V8SF 0 "register_operand" "=x") (float_extend:V8SF (vec_select:<ssehalfvecmode> - (match_operand:VHFBF_256 1 "memory_operand" "m") + (match_operand:VHFBF_256 1 "memory_operand" "jm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -31266,7 +31266,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x") (float_extend:V4SF (vec_select:<ssehalfvecmode> - (match_operand:VHFBF_128 1 "memory_operand" "m") + (match_operand:VHFBF_128 1 "memory_operand" "jm") (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))] "TARGET_AVXNECONVERT" @@ -31278,7 +31278,7 @@ [(set (match_operand:V8SF 0 "register_operand" "=x") (float_extend:V8SF (vec_select:<ssehalfvecmode> - (match_operand:VHFBF_256 1 "memory_operand" "m") + (match_operand:VHFBF_256 1 "memory_operand" "jm") (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7) (const_int 9) (const_int 11) -- 2.31.1