| Message ID | 20240726163719.1667923-1-jesse@rivosinc.com |
|---|---|
| Headers | show |
| Series | RISC-V: Detect and report speed of unaligned vector accesses | expand |
On Fri, Jul 26, 2024 at 9:37 AM Jesse Taube <jesse@rivosinc.com> wrote: > > Run a unaligned vector access to test if the system supports > vector unaligned access. Add the result to a new key in hwprobe. > This is useful for usermode to know if vector misaligned accesses are > supported and if they are faster or slower than equivalent byte accesses. > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com>
On Fri, Jul 26, 2024 at 9:37 AM Jesse Taube <jesse@rivosinc.com> wrote: > > Detect if vector misaligned accesses are faster or slower than > equivalent vector byte accesses. This is useful for usermode to know > whether vector byte accesses or vector misaligned accesses have a better > bandwidth for operations like memcpy. > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com>
On Fri, Jul 26, 2024 at 9:37 AM Jesse Taube <jesse@rivosinc.com> wrote: > > Document key for reporting the speed of unaligned vector accesses. > The descriptions are the same as the scalar equivalent values. > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com>
Adds support for detecting and reporting the speed of unaligned vector accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe adds Zicclsm to cpufeature and fixes the check for scalar unaligned emulated all CPUs. The vec_misaligned_speed key keeps the same format as the scalar unaligned access speed key. This set does not emulate unaligned vector accesses on CPUs that do not support them. Only reports if userspace can run them and speed of unaligned vector accesses if supported. The Zicclsm is patches are no longer related to this set. Changes in v6: Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs") Jesse Taube (8): RISC-V: Add Zicclsm to cpufeature and hwprobe dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Check scalar unaligned access on all CPUs RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect unaligned vector accesses supported RISC-V: Report vector unaligned access speed hwprobe RISC-V: hwprobe: Document unaligned vector perf key Documentation/arch/riscv/hwprobe.rst | 21 +++ .../devicetree/bindings/riscv/extensions.yaml | 7 + arch/riscv/Kconfig | 57 ++++++- arch/riscv/include/asm/cpufeature.h | 10 +- arch/riscv/include/asm/entry-common.h | 11 -- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/vector.h | 2 + arch/riscv/include/uapi/asm/hwprobe.h | 6 + arch/riscv/kernel/Makefile | 3 +- arch/riscv/kernel/copy-unaligned.h | 5 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/fpu.S | 4 +- arch/riscv/kernel/sys_hwprobe.c | 42 +++++ arch/riscv/kernel/traps_misaligned.c | 131 +++++++++++++-- arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++- arch/riscv/kernel/vec-copy-unaligned.S | 58 +++++++ arch/riscv/kernel/vector.c | 2 +- 18 files changed, 481 insertions(+), 38 deletions(-) create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S