| Message ID | 20240512121633.1632597-8-jonas@kwiboo.se |
|---|---|
| State | Superseded |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: pinctrl: Minor fixes and add support for pinmux status cmd | expand |
On 2024/5/12 20:16, Jonas Karlman wrote: > Use the pinctrl pin offset to get_gpio_mux() to remove the bank num > dependency and instead only use the bank num to assign a bank name. > > Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the > pinctrl pin offset typically is aligned to 32. > > However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl > pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin > aligned bank num. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/gpio/rk_gpio.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c > index 8f8f21acc2f5..a3691ad25b78 100644 > --- a/drivers/gpio/rk_gpio.c > +++ b/drivers/gpio/rk_gpio.c > @@ -35,7 +35,7 @@ enum { > struct rockchip_gpio_priv { > void __iomem *regs; > struct udevice *pinctrl; > - int bank; > + int pfc_offset; > char name[2]; > u32 version; > }; > @@ -109,7 +109,8 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) > int ret; > > if (CONFIG_IS_ENABLED(PINCTRL)) { > - ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); > + ret = pinctrl_get_gpio_mux(priv->pinctrl, -1, > + priv->pfc_offset + offset); > if (ret < 0) > return ret; > else if (ret != RK_FUNC_GPIO) > @@ -187,7 +188,7 @@ static int rockchip_gpio_probe(struct udevice *dev) > struct rockchip_gpio_priv *priv = dev_get_priv(dev); > struct ofnode_phandle_args args; > char *end; > - int ret; > + int bank, ret; > > priv->regs = dev_read_addr_ptr(dev); > > @@ -200,7 +201,8 @@ static int rockchip_gpio_probe(struct udevice *dev) > 0, &args); > if (!ret) { > uc_priv->gpio_count = args.args[2]; > - priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK; > + bank = DIV_ROUND_UP(args.args[1], ROCKCHIP_GPIOS_PER_BANK); > + priv->pfc_offset = args.args[1]; > > if (CONFIG_IS_ENABLED(PINCTRL)) { > ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, > @@ -211,11 +213,12 @@ static int rockchip_gpio_probe(struct udevice *dev) > } > } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { > uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; > - ret = dev_read_alias_seq(dev, &priv->bank); > + ret = dev_read_alias_seq(dev, &bank); > if (ret) { > end = strrchr(dev->name, '@'); > - priv->bank = trailing_strtoln(dev->name, end); > + bank = trailing_strtoln(dev->name, end); > } > + priv->pfc_offset = bank * ROCKCHIP_GPIOS_PER_BANK; > > if (CONFIG_IS_ENABLED(PINCTRL)) { > ret = uclass_first_device_err(UCLASS_PINCTRL, > @@ -227,7 +230,7 @@ static int rockchip_gpio_probe(struct udevice *dev) > return ret; > } > > - priv->name[0] = 'A' + priv->bank; > + priv->name[0] = 'A' + bank; > uc_priv->bank_name = priv->name; > > priv->version = readl(priv->regs + VER_ID_V2);
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 8f8f21acc2f5..a3691ad25b78 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -35,7 +35,7 @@ enum { struct rockchip_gpio_priv { void __iomem *regs; struct udevice *pinctrl; - int bank; + int pfc_offset; char name[2]; u32 version; }; @@ -109,7 +109,8 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) int ret; if (CONFIG_IS_ENABLED(PINCTRL)) { - ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); + ret = pinctrl_get_gpio_mux(priv->pinctrl, -1, + priv->pfc_offset + offset); if (ret < 0) return ret; else if (ret != RK_FUNC_GPIO) @@ -187,7 +188,7 @@ static int rockchip_gpio_probe(struct udevice *dev) struct rockchip_gpio_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; char *end; - int ret; + int bank, ret; priv->regs = dev_read_addr_ptr(dev); @@ -200,7 +201,8 @@ static int rockchip_gpio_probe(struct udevice *dev) 0, &args); if (!ret) { uc_priv->gpio_count = args.args[2]; - priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK; + bank = DIV_ROUND_UP(args.args[1], ROCKCHIP_GPIOS_PER_BANK); + priv->pfc_offset = args.args[1]; if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, @@ -211,11 +213,12 @@ static int rockchip_gpio_probe(struct udevice *dev) } } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; - ret = dev_read_alias_seq(dev, &priv->bank); + ret = dev_read_alias_seq(dev, &bank); if (ret) { end = strrchr(dev->name, '@'); - priv->bank = trailing_strtoln(dev->name, end); + bank = trailing_strtoln(dev->name, end); } + priv->pfc_offset = bank * ROCKCHIP_GPIOS_PER_BANK; if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_first_device_err(UCLASS_PINCTRL, @@ -227,7 +230,7 @@ static int rockchip_gpio_probe(struct udevice *dev) return ret; } - priv->name[0] = 'A' + priv->bank; + priv->name[0] = 'A' + bank; uc_priv->bank_name = priv->name; priv->version = readl(priv->regs + VER_ID_V2);
Use the pinctrl pin offset to get_gpio_mux() to remove the bank num dependency and instead only use the bank num to assign a bank name. Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the pinctrl pin offset typically is aligned to 32. However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin aligned bank num. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/gpio/rk_gpio.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)