| Message ID | 20240709123629.666151-7-karol.kolacinski@intel.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | ice: Implement PTP support for E830 devices | expand |
On Tue, Jul 09, 2024 at 02:34:55PM +0200, Karol Kolacinski wrote: > From: Michal Michalik <michal.michalik@intel.com> > > Add specific functions and definitions for E830 devices to enable > PTP support. > Introduce new PHY model ICE_PHY_E830. > E830 devices support direct write to GLTSYN_ registers without shadow > registers and 64 bit read of PHC time. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Co-developed-by: Milena Olech <milena.olech@intel.com> > Signed-off-by: Milena Olech <milena.olech@intel.com> > Co-developed-by: Paul Greenwalt <paul.greenwalt@intel.com> > Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> > Signed-off-by: Michal Michalik <michal.michalik@intel.com> > Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> ... > diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c > index 009716a12a26..005054439204 100644 > --- a/drivers/net/ethernet/intel/ice/ice_common.c > +++ b/drivers/net/ethernet/intel/ice/ice_common.c > @@ -307,6 +307,17 @@ bool ice_is_e825c(struct ice_hw *hw) > } > } > > +/** > + * ice_is_e830 > + * @hw: pointer to the hardware structure > + * > + * returns true if the device is E830 based, false if not. Hi Michal, Karol, all, Please consider documenting return values using a "Return:" or "Returns:" section. Flagged by: kernel-doc -none -Wall > + */ > +bool ice_is_e830(const struct ice_hw *hw) > +{ > + return hw->mac_type == ICE_MAC_E830; > +} > + > /** > * ice_clear_pf_cfg - Clear PF configuration > * @hw: pointer to the hardware structure ... > diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > index 06500028c760..3a5dd65a9a80 100644 > --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > @@ -327,6 +327,7 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; > #define ICE_E810_PLL_FREQ 812500000 > #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL > #define ICE_E810_OUT_PROP_DELAY_NS 1 > +#define ICE_E810_E830_SYNC_DELAY 0 > #define ICE_E825C_OUT_PROP_DELAY_NS 11 > > /* Device agnostic functions */ > @@ -673,18 +674,21 @@ static inline bool ice_is_primary(struct ice_hw *hw) > /* E810 timer command register */ > #define E810_ETH_GLTSYN_CMD 0x03000344 > > +/* E830 timer command register */ > +#define E830_ETH_GLTSYN_CMD 0x00088814 > + > +/* E810 PHC time register */ > +#define E830_GLTSYN_TIME_L(_tmr_idx) (0x0008A000 + 0x1000 * (_tmr_idx)) > + > /* Source timer incval macros */ > #define INCVAL_HIGH_M 0xFF > > -/* Timestamp block macros */ > +/* PHY 40b registers macros */ > +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) > +#define PHY_EXT_40B_HIGH_M GENMASK(39, 32) > +#define PHY_40B_LOW_M GENMASK(7, 0) > +#define PHY_40B_HIGH_M GENMASK(39, 8) I think that GENMASK_ULL needs to be used here to avoid breakage on systems with 32bit unsigned long. > #define TS_VALID BIT(0) > -#define TS_LOW_M 0xFFFFFFFF > -#define TS_HIGH_M 0xFF > -#define TS_HIGH_S 32 > - > -#define TS_PHY_LOW_M 0xFF > -#define TS_PHY_HIGH_M 0xFFFFFFFF > -#define TS_PHY_HIGH_S 8 > > #define BYTES_PER_IDX_ADDR_L_U 8 > #define BYTES_PER_IDX_ADDR_L 4 ...
Hi Karol,
kernel test robot noticed the following build errors:
[auto build test ERROR on 529314adcbceca0e0ec72b3ea94fe4a54ae61ca6]
url: https://github.com/intel-lab-lkp/linux/commits/Karol-Kolacinski/ice-Implement-PTP-support-for-E830-devices/20240710-034725
base: 529314adcbceca0e0ec72b3ea94fe4a54ae61ca6
patch link: https://lore.kernel.org/r/20240709123629.666151-7-karol.kolacinski%40intel.com
patch subject: [PATCH iwl-next 1/4] ice: Implement PTP support for E830 devices
config: mips-allyesconfig (https://download.01.org/0day-ci/archive/20240711/202407110019.Tv1TxdCA-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240711/202407110019.Tv1TxdCA-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407110019.Tv1TxdCA-lkp@intel.com/
All errors (new ones prefixed by >>):
include/linux/compiler_types.h:510:9: note: in expansion of macro '_compiletime_assert'
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:9: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:9: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:75:17: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
75 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:76:56: note: in expansion of macro '__bf_shf'
76 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:115:17: note: in expansion of macro '__BF_FIELD_CHECK'
115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:19: note: in expansion of macro 'FIELD_PREP'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~
include/linux/bits.h:35:38: note: in expansion of macro '__GENMASK'
35 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.h:688:41: note: in expansion of macro 'GENMASK'
688 | #define PHY_EXT_40B_HIGH_M GENMASK(39, 32)
| ^~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:30: note: in expansion of macro 'PHY_EXT_40B_HIGH_M'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/bits.h:8:31: warning: left shift count >= width of type [-Wshift-count-overflow]
8 | (((~_UL(0)) - (_UL(1) << (l)) + 1) & \
| ^~
include/linux/bitfield.h:45:38: note: in definition of macro '__bf_shf'
45 | #define __bf_shf(x) (__builtin_ffsll(x) - 1)
| ^
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:19: note: in expansion of macro 'FIELD_PREP'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~
include/linux/bits.h:35:38: note: in expansion of macro '__GENMASK'
35 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.h:688:41: note: in expansion of macro 'GENMASK'
688 | #define PHY_EXT_40B_HIGH_M GENMASK(39, 32)
| ^~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:30: note: in expansion of macro 'PHY_EXT_40B_HIGH_M'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/bits.h:9:19: warning: right shift count is negative [-Wshift-count-negative]
9 | (~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bitfield.h:45:38: note: in definition of macro '__bf_shf'
45 | #define __bf_shf(x) (__builtin_ffsll(x) - 1)
| ^
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:19: note: in expansion of macro 'FIELD_PREP'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~
include/linux/bits.h:35:38: note: in expansion of macro '__GENMASK'
35 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.h:688:41: note: in expansion of macro 'GENMASK'
688 | #define PHY_EXT_40B_HIGH_M GENMASK(39, 32)
| ^~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:30: note: in expansion of macro 'PHY_EXT_40B_HIGH_M'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/bits.h:8:31: warning: left shift count >= width of type [-Wshift-count-overflow]
8 | (((~_UL(0)) - (_UL(1) << (l)) + 1) & \
| ^~
include/linux/bitfield.h:116:63: note: in definition of macro 'FIELD_PREP'
116 | ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
| ^~~~~
include/linux/bits.h:35:38: note: in expansion of macro '__GENMASK'
35 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.h:688:41: note: in expansion of macro 'GENMASK'
688 | #define PHY_EXT_40B_HIGH_M GENMASK(39, 32)
| ^~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:30: note: in expansion of macro 'PHY_EXT_40B_HIGH_M'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/bits.h:9:19: warning: right shift count is negative [-Wshift-count-negative]
9 | (~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bitfield.h:116:63: note: in definition of macro 'FIELD_PREP'
116 | ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
| ^~~~~
include/linux/bits.h:35:38: note: in expansion of macro '__GENMASK'
35 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.h:688:41: note: in expansion of macro 'GENMASK'
688 | #define PHY_EXT_40B_HIGH_M GENMASK(39, 32)
| ^~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:30: note: in expansion of macro 'PHY_EXT_40B_HIGH_M'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c: In function 'ice_read_ptp_tstamp_eth56g.isra':
>> include/linux/compiler_types.h:510:45: error: call to '__compiletime_assert_978' declared with attribute error: FIELD_PREP: mask is not constant
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
include/linux/compiler_types.h:491:25: note: in definition of macro '__compiletime_assert'
491 | prefix ## suffix(); \
| ^~~~~~
include/linux/compiler_types.h:510:9: note: in expansion of macro '_compiletime_assert'
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:65:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
65 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:115:17: note: in expansion of macro '__BF_FIELD_CHECK'
115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:1511:19: note: in expansion of macro 'FIELD_PREP'
1511 | *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
| ^~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c: In function 'ice_read_phy_tstamp_e810.isra':
include/linux/compiler_types.h:510:45: error: call to '__compiletime_assert_1260' declared with attribute error: FIELD_PREP: mask is not constant
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
include/linux/compiler_types.h:491:25: note: in definition of macro '__compiletime_assert'
491 | prefix ## suffix(); \
| ^~~~~~
include/linux/compiler_types.h:510:9: note: in expansion of macro '_compiletime_assert'
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:65:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
65 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:115:17: note: in expansion of macro '__BF_FIELD_CHECK'
115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:4948:19: note: in expansion of macro 'FIELD_PREP'
4948 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c: In function 'ice_read_phy_tstamp_e82x.isra':
include/linux/compiler_types.h:510:45: error: call to '__compiletime_assert_1160' declared with attribute error: FIELD_PREP: mask is not constant
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
include/linux/compiler_types.h:491:25: note: in definition of macro '__compiletime_assert'
491 | prefix ## suffix(); \
| ^~~~~~
include/linux/compiler_types.h:510:9: note: in expansion of macro '_compiletime_assert'
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:65:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
65 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:115:17: note: in expansion of macro '__BF_FIELD_CHECK'
115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:3193:19: note: in expansion of macro 'FIELD_PREP'
3193 | *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
| ^~~~~~~~~~
In function 'ice_read_phy_tstamp_e830',
inlined from 'ice_read_phy_tstamp' at drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5874:10:
include/linux/compiler_types.h:510:45: error: call to '__compiletime_assert_1295' declared with attribute error: FIELD_PREP: mask is not constant
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
include/linux/compiler_types.h:491:25: note: in definition of macro '__compiletime_assert'
491 | prefix ## suffix(); \
| ^~~~~~
include/linux/compiler_types.h:510:9: note: in expansion of macro '_compiletime_assert'
510 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:65:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
65 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:115:17: note: in expansion of macro '__BF_FIELD_CHECK'
115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5436:19: note: in expansion of macro 'FIELD_PREP'
5436 | *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
| ^~~~~~~~~~
vim +/__compiletime_assert_978 +510 include/linux/compiler_types.h
eb5c2d4b45e3d2 Will Deacon 2020-07-21 496
eb5c2d4b45e3d2 Will Deacon 2020-07-21 497 #define _compiletime_assert(condition, msg, prefix, suffix) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21 498 __compiletime_assert(condition, msg, prefix, suffix)
eb5c2d4b45e3d2 Will Deacon 2020-07-21 499
eb5c2d4b45e3d2 Will Deacon 2020-07-21 500 /**
eb5c2d4b45e3d2 Will Deacon 2020-07-21 501 * compiletime_assert - break build and emit msg if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21 502 * @condition: a compile-time constant condition to check
eb5c2d4b45e3d2 Will Deacon 2020-07-21 503 * @msg: a message to emit if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21 504 *
eb5c2d4b45e3d2 Will Deacon 2020-07-21 505 * In tradition of POSIX assert, this macro will break the build if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21 506 * supplied condition is *false*, emitting the supplied error message if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21 507 * compiler has support to do so.
eb5c2d4b45e3d2 Will Deacon 2020-07-21 508 */
eb5c2d4b45e3d2 Will Deacon 2020-07-21 509 #define compiletime_assert(condition, msg) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21 @510 _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
eb5c2d4b45e3d2 Will Deacon 2020-07-21 511
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index 009716a12a26..005054439204 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -307,6 +307,17 @@ bool ice_is_e825c(struct ice_hw *hw) } } +/** + * ice_is_e830 + * @hw: pointer to the hardware structure + * + * returns true if the device is E830 based, false if not. + */ +bool ice_is_e830(const struct ice_hw *hw) +{ + return hw->mac_type == ICE_MAC_E830; +} + /** * ice_clear_pf_cfg - Clear PF configuration * @hw: pointer to the hardware structure diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h index 27208a60cece..21a4d9734168 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.h +++ b/drivers/net/ethernet/intel/ice/ice_common.h @@ -279,6 +279,7 @@ bool ice_is_e810t(struct ice_hw *hw); bool ice_is_e822(struct ice_hw *hw); bool ice_is_e823(struct ice_hw *hw); bool ice_is_e825c(struct ice_hw *hw); +bool ice_is_e830(const struct ice_hw *hw); int ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, struct ice_aqc_txsched_elem_data *buf); diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h index 91cbae1eec89..646089f3e26c 100644 --- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h +++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h @@ -533,10 +533,14 @@ #define PFPM_WUS_MAG_M BIT(1) #define PFPM_WUS_MNG_M BIT(3) #define PFPM_WUS_FW_RST_WK_M BIT(31) +#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 +#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 #define E830_PRTMAC_CL01_PS_QNT 0x001E32A0 #define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0) #define E830_PRTMAC_CL01_QNT_THR 0x001E3320 #define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0) +#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32)) +#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32)) #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 30ebf3efc86b..b1a8ec549f6a 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -309,6 +309,15 @@ ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts) /* Read the system timestamp pre PHC read */ ptp_read_system_prets(sts); + if (ice_is_e830(hw)) { + u64 clk_time = rd64(hw, E830_GLTSYN_TIME_L(tmr_idx)); + + /* Read the system timestamp post PHC read */ + ptp_read_system_postts(sts); + + return clk_time; + } + lo = rd32(hw, GLTSYN_TIME_L(tmr_idx)); /* Read the system timestamp post PHC read */ @@ -2481,7 +2490,7 @@ static void ice_ptp_set_caps(struct ice_pf *pf) info->enable = ice_ptp_gpio_enable; info->verify = ice_verify_pin; - if (ice_is_e810(&pf->hw)) + if (ice_is_e810(&pf->hw) || ice_is_e830(&pf->hw)) ice_ptp_set_funcs_e810(pf); else ice_ptp_set_funcs_e82x(pf); diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 1d6b05554b08..6ad23665bbd1 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -874,6 +874,17 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) ice_flush(hw); } +/** + * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay + * @hw: pointer to HW struct + * @delay: delay between PHC and PHY SYNC command execution in nanoseconds + */ +static void ice_ptp_cfg_sync_delay(struct ice_hw *hw, u32 delay) +{ + wr32(hw, GLTSYN_SYNC_DLAY, delay); + ice_flush(hw); +} + /* 56G PHY device functions * * The following functions operate on devices with the ETH 56G PHY. @@ -1497,7 +1508,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -3178,7 +3190,8 @@ ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -4932,7 +4945,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) /* For E810 devices, the timestamp is reported with the lower 32 bits * in the low register, and the upper 8 bits in the high register. */ - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); return 0; } @@ -4995,8 +5009,7 @@ static int ice_ptp_init_phc_e810(struct ice_hw *hw) u8 tmr_idx; int err; - /* Ensure synchronization delay is zero */ - wr32(hw, GLTSYN_SYNC_DLAY, 0); + ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), @@ -5324,11 +5337,140 @@ static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) ptp->ports_per_phy = 4; } +/* E830 functions + * + * The following functions operate on the E830 series devices. + * + */ + +/** + * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization + * @hw: pointer to HW struct + * + * Perform E830-specific PTP hardware clock initialization steps. + */ +static int ice_ptp_init_phc_e830(struct ice_hw *hw) +{ + ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); + return 0; +} + +/** + * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change + * @hw: pointer to HW struct + * @incval: The new 40bit increment value to prepare + * + * Prepare the PHY port for a new increment value by programming the PHC + * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is + * completed by FW automatically. + */ +static int ice_ptp_write_direct_incval_e830(struct ice_hw *hw, u64 incval) +{ + u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; + + wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); + wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); + + return 0; +} + +/** + * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time + * @hw: Board private structure + * @time: Time to initialize the PHY port clock to + * + * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the + * initial clock time. The time will not actually be programmed until the + * driver issues an ICE_PTP_INIT_TIME command. + * + * The time value is the upper 32 bits of the PHY timer, usually in units of + * nominal nanoseconds. + */ +static int ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time) +{ + u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; + + wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); + wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); + wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); + + return 0; +} + +/** + * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command + * @hw: pointer to HW struct + * @cmd: Command to be sent to the port + * + * Prepare the external PHYs connected to this device for a timer sync + * command. + */ +static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) +{ + u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); + + return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); +} + +/** + * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY + * @hw: pointer to the HW struct + * @lport: the lport to read from + * @idx: the timestamp index to read + * @tstamp: on return, the 40bit timestamp value + * + * Read a 40bit timestamp value out of the timestamp block of the external PHY + * on the E830 device. + */ +static int +ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) +{ + u32 hi, lo; + + hi = rd32(hw, E830_HIGH_TX_MEMORY_BANK(idx, lport)); + lo = rd32(hw, E830_LOW_TX_MEMORY_BANK(idx, lport)); + + /* For E830 devices, the timestamp is reported with the lower 32 bits + * in the low register, and the upper 8 bits in the high register. + */ + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); + + return 0; +} + +/** + * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register + * @hw: pointer to the HW struct + * @port: the PHY port to read + * @tstamp_ready: contents of the Tx memory status register + * + */ +static int +ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready) +{ + *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); + *tstamp_ready <<= 32; + *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); + + return 0; +} + +/** + * ice_ptp_init_phy_e830 - initialize PHY parameters + * @ptp: pointer to the PTP HW struct + */ +static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) +{ + ptp->phy_model = ICE_PHY_E830; + ptp->num_lports = 8; + ptp->ports_per_phy = 4; +} + /* Device agnostic functions * - * The following functions implement shared behavior common to both E822 and - * E810 devices, possibly calling a device specific implementation where - * necessary. + * The following functions implement shared behavior common to all devices, + * possibly calling a device specific implementation where necessary. */ /** @@ -5391,12 +5533,14 @@ void ice_ptp_init_hw(struct ice_hw *hw) { struct ice_ptp_hw *ptp = &hw->ptp; - if (ice_is_e822(hw) || ice_is_e823(hw)) - ice_ptp_init_phy_e82x(ptp); - else if (ice_is_e810(hw)) + if (ice_is_e810(hw)) ice_ptp_init_phy_e810(ptp); + else if (ice_is_e822(hw) || ice_is_e823(hw)) + ice_ptp_init_phy_e82x(ptp); else if (ice_is_e825c(hw)) ice_ptp_init_phy_e825c(hw); + else if (ice_is_e830(hw)) + ice_ptp_init_phy_e830(ptp); else ptp->phy_model = ICE_PHY_UNSUP; } @@ -5487,6 +5631,8 @@ static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) switch (ice_get_phy_model(hw)) { case ICE_PHY_E810: return ice_ptp_port_cmd_e810(hw, cmd); + case ICE_PHY_E830: + return ice_ptp_port_cmd_e830(hw, cmd); default: break; } @@ -5557,6 +5703,10 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; /* Source timers */ + /* For E830 we don't need to use shadow registers, its automatic */ + if (hw->ptp.phy_model == ICE_PHY_E830) + return ice_ptp_write_direct_phc_time_e830(hw, time); + wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); @@ -5605,6 +5755,10 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; + /* For E830 we don't need to use shadow registers, its automatic */ + if (hw->ptp.phy_model == ICE_PHY_E830) + return ice_ptp_write_direct_incval_e830(hw, incval); + /* Shadow Adjust */ wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); @@ -5712,12 +5866,14 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) { switch (ice_get_phy_model(hw)) { - case ICE_PHY_ETH56G: - return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); case ICE_PHY_E810: return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); case ICE_PHY_E82X: return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); + case ICE_PHY_E830: + return ice_read_phy_tstamp_e830(hw, block, idx, tstamp); + case ICE_PHY_ETH56G: + return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); default: return -EOPNOTSUPP; } @@ -5834,12 +5990,14 @@ int ice_ptp_init_phc(struct ice_hw *hw) (void)rd32(hw, GLTSYN_STAT(src_idx)); switch (ice_get_phy_model(hw)) { - case ICE_PHY_ETH56G: - return ice_ptp_init_phc_eth56g(hw); case ICE_PHY_E810: return ice_ptp_init_phc_e810(hw); case ICE_PHY_E82X: return ice_ptp_init_phc_e82x(hw); + case ICE_PHY_E830: + return ice_ptp_init_phc_e830(hw); + case ICE_PHY_ETH56G: + return ice_ptp_init_phc_eth56g(hw); default: return -EOPNOTSUPP; } @@ -5859,15 +6017,18 @@ int ice_ptp_init_phc(struct ice_hw *hw) int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) { switch (ice_get_phy_model(hw)) { - case ICE_PHY_ETH56G: - return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, - tstamp_ready); case ICE_PHY_E810: return ice_get_phy_tx_tstamp_ready_e810(hw, block, tstamp_ready); case ICE_PHY_E82X: return ice_get_phy_tx_tstamp_ready_e82x(hw, block, tstamp_ready); + case ICE_PHY_E830: + return ice_get_phy_tx_tstamp_ready_e830(hw, block, + tstamp_ready); + case ICE_PHY_ETH56G: + return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, + tstamp_ready); break; default: return -EOPNOTSUPP; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 06500028c760..3a5dd65a9a80 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -327,6 +327,7 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; #define ICE_E810_PLL_FREQ 812500000 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL #define ICE_E810_OUT_PROP_DELAY_NS 1 +#define ICE_E810_E830_SYNC_DELAY 0 #define ICE_E825C_OUT_PROP_DELAY_NS 11 /* Device agnostic functions */ @@ -673,18 +674,21 @@ static inline bool ice_is_primary(struct ice_hw *hw) /* E810 timer command register */ #define E810_ETH_GLTSYN_CMD 0x03000344 +/* E830 timer command register */ +#define E830_ETH_GLTSYN_CMD 0x00088814 + +/* E810 PHC time register */ +#define E830_GLTSYN_TIME_L(_tmr_idx) (0x0008A000 + 0x1000 * (_tmr_idx)) + /* Source timer incval macros */ #define INCVAL_HIGH_M 0xFF -/* Timestamp block macros */ +/* PHY 40b registers macros */ +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) +#define PHY_EXT_40B_HIGH_M GENMASK(39, 32) +#define PHY_40B_LOW_M GENMASK(7, 0) +#define PHY_40B_HIGH_M GENMASK(39, 8) #define TS_VALID BIT(0) -#define TS_LOW_M 0xFFFFFFFF -#define TS_HIGH_M 0xFF -#define TS_HIGH_S 32 - -#define TS_PHY_LOW_M 0xFF -#define TS_PHY_HIGH_M 0xFFFFFFFF -#define TS_PHY_HIGH_S 8 #define BYTES_PER_IDX_ADDR_L_U 8 #define BYTES_PER_IDX_ADDR_L 4 @@ -708,6 +712,11 @@ static inline bool ice_is_primary(struct ice_hw *hw) #define LOW_TX_MEMORY_BANK_START 0x03090000 #define HIGH_TX_MEMORY_BANK_START 0x03090004 +#define E830_LOW_TX_MEMORY_BANK(slot, port) \ + (E830_PRTTSYN_TXTIME_L(slot) + 0x8 * (port)) +#define E830_HIGH_TX_MEMORY_BANK(slot, port) \ + (E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port)) + /* SMA controller pin control */ #define ICE_SMA1_DIR_EN BIT(4) #define ICE_SMA1_TX_EN BIT(5) diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h index b6bc2de53b0a..501994f057a7 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -866,6 +866,7 @@ enum ice_phy_model { ICE_PHY_E810 = 1, ICE_PHY_E82X, ICE_PHY_ETH56G, + ICE_PHY_E830, }; /* Global Link Topology */