| Message ID | 20240619-msm8226-cpufreq-v1-0-85143f5291d1@lucaweiss.eu |
|---|---|
| Headers | show |
| Series | Add CPU frequency scaling support for MSM8226 | expand |
On Wed, Jun 19, 2024 at 11:02:49PM GMT, Luca Weiss wrote: > Add a node for the a7pll with its frequencies. With this we can use the > apcs-kpss-global driver for the apcs node and use the apcs to scale the > CPU frequency according to the opp-table. > > At the same time unfortunately we need to provide the gcc node xo_board > instead of the XO via rpmcc since otherwise we'll have a circular > dependency between apcs, gcc and the rpm. But it should be fine, isn't it? Clock controllers can handle orphaned clocks. The xo_board is really a hack and should eventually be removed. > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > ---
On Wed, Jun 19, 2024 at 11:02:50PM GMT, Luca Weiss wrote: > Add cooling-maps for the CPU thermal zones so the driver can actually do > something when the CPU temperature rises too much. > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > --- > arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Wed, Jun 19, 2024 at 11:02:51PM GMT, Luca Weiss wrote: > Since we now have the apcs set up as a mailbox provider, let's use the > interface for all drivers where possible. > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > --- > arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Donnerstag, 20. Juni 2024 22:54:37 MESZ Dmitry Baryshkov wrote: > On Wed, Jun 19, 2024 at 11:02:49PM GMT, Luca Weiss wrote: > > Add a node for the a7pll with its frequencies. With this we can use the > > apcs-kpss-global driver for the apcs node and use the apcs to scale the > > CPU frequency according to the opp-table. > > > > At the same time unfortunately we need to provide the gcc node xo_board > > instead of the XO via rpmcc since otherwise we'll have a circular > > dependency between apcs, gcc and the rpm. > > But it should be fine, isn't it? Clock controllers can handle orphaned > clocks. > > The xo_board is really a hack and should eventually be removed. I can check again what happened but pretty sure there were some issues with this still being rpmcc. But there were also some clock issues with apcs-as-syscon usage (that's the main reason for my influx of patches regarding this topic), so maybe with the apcs one solved that one's also fine. I'll check again! > > > > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > > --- > >
On 19.06.2024 11:02 PM, Luca Weiss wrote: > Add a node for the a7pll with its frequencies. With this we can use the > apcs-kpss-global driver for the apcs node and use the apcs to scale the > CPU frequency according to the opp-table. > > At the same time unfortunately we need to provide the gcc node xo_board > instead of the XO via rpmcc since otherwise we'll have a circular > dependency between apcs, gcc and the rpm. Hm.. thinking of a solution to that, should we maybe split the mux/clk part of APCS into a subnode and bind the clk device to that? Dmitry, Bjorn, thoughts? [...] > + > + opp-600000000 { Can't find this one in the random msm-3.10 I have > + opp-hz = /bits/ 64 <600000000>; > + }; > + > + opp-787200000 { > + opp-hz = /bits/ 64 <787200000>; > + }; > + > + /* Higher CPU frequencies need speedbin support */ 1190400 kHz seems to also be a supported-across-the-board one.. unless the watch edition shuffled things around with a newer tree > + }; > + > pmu { > compatible = "arm,cortex-a7-pmu"; > interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | > @@ -231,9 +262,75 @@ intc: interrupt-controller@f9000000 { > #interrupt-cells = <3>; > }; > > - apcs: syscon@f9011000 { > - compatible = "syscon"; > + apcs: mailbox@f9011000 { > + compatible = "qcom,msm8226-apcs-kpss-global", > + "qcom,msm8916-apcs-kpss-global", "syscon"; > reg = <0xf9011000 0x1000>; > + #mbox-cells = <1>; > + clocks = <&a7pll>, <&gcc GPLL0_VOTE>; > + clock-names = "pll", "aux"; > + #clock-cells = <0>; > + }; > + > + a7pll: clock@f9016000 { > + compatible = "qcom,msm8226-a7pll"; > + reg = <0xf9016000 0x40>; > + #clock-cells = <0>; > + clocks = <&xo_board>; > + clock-names = "xo"; > + operating-points-v2 = <&a7pll_opp_table>; > + > + a7pll_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-768000000 { > + opp-hz = /bits/ 64 <768000000>; > + }; Looks like scaling this PLL should also scale some voltage domains: CPR (fed by pm8226_s2) and MX Perhaps hook up MX to this one for now and add CPR to the CPU nodes( & OPP table) after that is brought up Konrad
On 19.06.2024 11:02 PM, Luca Weiss wrote: > Add cooling-maps for the CPU thermal zones so the driver can actually do > something when the CPU temperature rises too much. > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > --- Very cool, thanks Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 19.06.2024 11:02 PM, Luca Weiss wrote: > Since we now have the apcs set up as a mailbox provider, let's use the > interface for all drivers where possible. > > Signed-off-by: Luca Weiss <luca@lucaweiss.eu> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Wed, 19 Jun 2024 23:02:44 +0200, Luca Weiss wrote: > Apart from a bunch of bindings updates, add support for the a7pll found > on the SoC and wire up everything in the dtsi. And finally switch over > to using apcs via mbox interface to stop using the apcs via syscon. > > Only a limited list of CPU frequencies are supported for now, higher > ones require speedbin support which I plan to work on after this lands. > > [...] Applied, thanks! [5/7] ARM: dts: qcom: msm8226: Add CPU frequency scaling support commit: 02f2ddaa1a78cbebd4255f78260781b404225170 [6/7] ARM: dts: qcom: msm8226: Hook up CPU cooling commit: 807dfab845209062e4d268157cfbf0ba46652df7 [7/7] ARM: dts: qcom: msm8226: Convert APCS usages to mbox interface commit: c47dd4a87160fd604577aca41ca8b3391b5c5d3e Best regards,
Apart from a bunch of bindings updates, add support for the a7pll found on the SoC and wire up everything in the dtsi. And finally switch over to using apcs via mbox interface to stop using the apcs via syscon. Only a limited list of CPU frequencies are supported for now, higher ones require speedbin support which I plan to work on after this lands. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> --- Luca Weiss (7): dt-bindings: mailbox: qcom: add compatible for MSM8226 SoC dt-bindings: clock: qcom,a53pll: Allow opp-table subnode dt-bindings: clock: qcom,a53pll: Add msm8226-a7pll compatible clk: qcom: a53-pll: Add MSM8226 a7pll support ARM: dts: qcom: msm8226: Add CPU frequency scaling support ARM: dts: qcom: msm8226: Hook up CPU cooling ARM: dts: qcom: msm8226: Convert APCS usages to mbox interface .../devicetree/bindings/clock/qcom,a53pll.yaml | 4 + .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 134 ++++++++++++++++++++- drivers/clk/qcom/a53-pll.c | 1 + 4 files changed, 134 insertions(+), 6 deletions(-) --- base-commit: 0efa3123a1658dbafdace0bfcdcc4f34eebc7f9f change-id: 20240619-msm8226-cpufreq-788b0bf0256a Best regards,