| Message ID | 20240428142406.28445-1-heesub@gmail.com |
|---|---|
| State | Accepted |
| Commit | 2ae44edf1d341db1a0102150e02f463c90d657a0 |
| Delegated to: | Patrice Chotard |
| Headers | show |
| Series | [1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK | expand |
On 4/28/24 16:24, Heesub Shin wrote: > Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to > 125, 62.5 and 62.5Mhz in respectively. > > Signed-off-by: Heesub Shin <heesub@gmail.com> > --- > arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > index b780dbd95e..d07fdcf4bc 100644 > --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > @@ -115,11 +115,11 @@ > bootph-all; > }; > > - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ > + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ > pll4: st,pll@3 { > compatible = "st,stm32mp1-pll"; > reg = <3>; > - cfg = < 3 98 5 7 7 PQR(1,1,1) >; > + cfg = < 3 124 5 9 9 PQR(1,1,1) >; > bootph-all; > }; > }; Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote: > Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to > 125, 62.5 and 62.5Mhz in respectively. > > Signed-off-by: Heesub Shin <heesub@gmail.com> > --- > arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > index b780dbd95e..d07fdcf4bc 100644 > --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi > @@ -115,11 +115,11 @@ > bootph-all; > }; > > - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ > + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ > pll4: st,pll@3 { > compatible = "st,stm32mp1-pll"; > reg = <3>; > - cfg = < 3 98 5 7 7 PQR(1,1,1) >; > + cfg = < 3 124 5 9 9 PQR(1,1,1) >; > bootph-all; > }; > }; Applied to u-boot-stm32/next Thanks Patrice
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; }; - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + cfg = < 3 124 5 9 9 PQR(1,1,1) >; bootph-all; }; };
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively. Signed-off-by: Heesub Shin <heesub@gmail.com> --- arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)