| Message ID | 20240512225738.528917-2-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | Add DF_LIVE_SUBREG data and apply to IRA and LRA | expand |
Juzhe-Zhong <juzhe.zhong@rivai.ai> writes: > --- > gcc/common.opt | 4 ++++ > gcc/common.opt.urls | 3 +++ > gcc/doc/invoke.texi | 8 ++++++++ > gcc/opts.cc | 1 + > 4 files changed, 16 insertions(+) > > diff --git a/gcc/common.opt b/gcc/common.opt > index 40cab3cb36a..5710e817abe 100644 > --- a/gcc/common.opt > +++ b/gcc/common.opt > @@ -2163,6 +2163,10 @@ fira-share-spill-slots > Common Var(flag_ira_share_spill_slots) Init(1) Optimization > Share stack slots for spilled pseudo-registers. > > +ftrack-subreg-liveness > +Common Var(flag_track_subreg_liveness) Init(0) Optimization > +Track subreg liveness information. > + > fira-verbose= > Common RejectNegative Joined UInteger Var(flag_ira_verbose) Init(5) > -fira-verbose=<number> Control IRA's level of diagnostic messages. > diff --git a/gcc/common.opt.urls b/gcc/common.opt.urls > index f71ed80a34b..59f27a6f7c6 100644 > --- a/gcc/common.opt.urls > +++ b/gcc/common.opt.urls > @@ -880,6 +880,9 @@ UrlSuffix(gcc/Optimize-Options.html#index-fira-share-save-slots) > fira-share-spill-slots > UrlSuffix(gcc/Optimize-Options.html#index-fira-share-spill-slots) > > +ftrack-subreg-liveness > +UrlSuffix(gcc/Optimize-Options.html#index-ftrack-subreg-liveness) > + > fira-verbose= > UrlSuffix(gcc/Developer-Options.html#index-fira-verbose) > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index ddcd5213f06..fbcde8aa745 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -13188,6 +13188,14 @@ Disable sharing of stack slots allocated for pseudo-registers. Each > pseudo-register that does not get a hard register gets a separate > stack slot, and as a result function stack frames are larger. > > +@opindex ftrack-subreg-liveness > +@item -ftrack-subreg-liveness > +Enable tracking subreg liveness information. This infomation allows IRA > +and LRA to support subreg coalesce feature which can improve the quality > +of register allocation. > + > +This option is enabled at level @option{-O3} for all targets. > + This is a good description, but some of these GCC terms might not be familiar to users. How about something like: ------------------------------------------------------------ Enable a more precise form of dataflow analysis. This analysis focuses on values that occupy multiple consecutive machine registers; examples of such values include complex numbers and small tuples of vectors. The analysis detects which parts of a value are in use at a given time and which parts are free to be reused for other things. Enabling the analysis can improve the quality of register allocation. This option is enabled at level @option{-O3} for all targets. ------------------------------------------------------------ It might be worth enabling at -O2 and above eventually, but I agree it makes sense to start with -O3. OK with that change if you agree and if there are no countersuggestions from others. Thanks, Richard > @opindex flra-remat > @item -flra-remat > Enable CFG-sensitive rematerialization in LRA. Instead of loading > diff --git a/gcc/opts.cc b/gcc/opts.cc > index 14d1767e48f..8fe3a213807 100644 > --- a/gcc/opts.cc > +++ b/gcc/opts.cc > @@ -698,6 +698,7 @@ static const struct default_options default_options_table[] = > { OPT_LEVELS_3_PLUS, OPT_funswitch_loops, NULL, 1 }, > { OPT_LEVELS_3_PLUS, OPT_fvect_cost_model_, NULL, VECT_COST_MODEL_DYNAMIC }, > { OPT_LEVELS_3_PLUS, OPT_fversion_loops_for_strides, NULL, 1 }, > + { OPT_LEVELS_3_PLUS, OPT_ftrack_subreg_liveness, NULL, 1 }, > > /* -O3 parameters. */ > { OPT_LEVELS_3_PLUS, OPT__param_max_inline_insns_auto_, NULL, 30 },
diff --git a/gcc/common.opt b/gcc/common.opt index 40cab3cb36a..5710e817abe 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2163,6 +2163,10 @@ fira-share-spill-slots Common Var(flag_ira_share_spill_slots) Init(1) Optimization Share stack slots for spilled pseudo-registers. +ftrack-subreg-liveness +Common Var(flag_track_subreg_liveness) Init(0) Optimization +Track subreg liveness information. + fira-verbose= Common RejectNegative Joined UInteger Var(flag_ira_verbose) Init(5) -fira-verbose=<number> Control IRA's level of diagnostic messages. diff --git a/gcc/common.opt.urls b/gcc/common.opt.urls index f71ed80a34b..59f27a6f7c6 100644 --- a/gcc/common.opt.urls +++ b/gcc/common.opt.urls @@ -880,6 +880,9 @@ UrlSuffix(gcc/Optimize-Options.html#index-fira-share-save-slots) fira-share-spill-slots UrlSuffix(gcc/Optimize-Options.html#index-fira-share-spill-slots) +ftrack-subreg-liveness +UrlSuffix(gcc/Optimize-Options.html#index-ftrack-subreg-liveness) + fira-verbose= UrlSuffix(gcc/Developer-Options.html#index-fira-verbose) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ddcd5213f06..fbcde8aa745 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13188,6 +13188,14 @@ Disable sharing of stack slots allocated for pseudo-registers. Each pseudo-register that does not get a hard register gets a separate stack slot, and as a result function stack frames are larger. +@opindex ftrack-subreg-liveness +@item -ftrack-subreg-liveness +Enable tracking subreg liveness information. This infomation allows IRA +and LRA to support subreg coalesce feature which can improve the quality +of register allocation. + +This option is enabled at level @option{-O3} for all targets. + @opindex flra-remat @item -flra-remat Enable CFG-sensitive rematerialization in LRA. Instead of loading diff --git a/gcc/opts.cc b/gcc/opts.cc index 14d1767e48f..8fe3a213807 100644 --- a/gcc/opts.cc +++ b/gcc/opts.cc @@ -698,6 +698,7 @@ static const struct default_options default_options_table[] = { OPT_LEVELS_3_PLUS, OPT_funswitch_loops, NULL, 1 }, { OPT_LEVELS_3_PLUS, OPT_fvect_cost_model_, NULL, VECT_COST_MODEL_DYNAMIC }, { OPT_LEVELS_3_PLUS, OPT_fversion_loops_for_strides, NULL, 1 }, + { OPT_LEVELS_3_PLUS, OPT_ftrack_subreg_liveness, NULL, 1 }, /* -O3 parameters. */ { OPT_LEVELS_3_PLUS, OPT__param_max_inline_insns_auto_, NULL, 30 },