| Message ID | 20240612100421.47938-1-harsimransingh.tungal@arm.com |
|---|---|
| State | Accepted |
| Commit | ee71d159aab66aef200c898606fcf51847d3377d |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm: dts: corstone1000: enable secondary cores for FVP | expand |
On Wed, Jun 12, 2024 at 11:04:21AM +0100, harsimransingh.tungal@arm.com wrote: > From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> > > Add the secondary cores nodes in the dts file > > Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> > Cc: Tom Rini <trini@konsulko.com> > Cc: Rui Miguel Silva <rui.silva@linaro.org> > --- > arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++ > arch/arm/dts/corstone1000.dtsi | 2 +- > 2 files changed, 26 insertions(+), 1 deletion(-) Can we move this to using OF_UPSTREAM instead? Thanks.
On Wed, 12 Jun 2024 11:04:21 +0100, harsimransingh.tungal@arm.com wrote: > Add the secondary cores nodes in the dts file > > Applied to u-boot/next, thanks!
> > From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> > > > > Add the secondary cores nodes in the dts file > > > > Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> > > Cc: Tom Rini <trini@konsulko.com> > > Cc: Rui Miguel Silva <rui.silva@linaro.org> > > --- > > arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++ > > arch/arm/dts/corstone1000.dtsi | 2 +- > > 2 files changed, 26 insertions(+), 1 deletion(-) > > Can we move this to using OF_UPSTREAM instead? Thanks. Thank you, we will be considering that. Harsimran Singh Tungal Cheers
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts index 26b0f1b3ce..3076fb9f34 100644 --- a/arch/arm/dts/corstone1000-fvp.dts +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -49,3 +49,28 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; + diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 1e0ec075e4..5d9d95b21c 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>;