diff mbox series

aarch64: Add vector floating point trunc pattern

Message ID 20240608030515.3693-1-quic_pzheng@quicinc.com
State New
Headers show
Series aarch64: Add vector floating point trunc pattern | expand

Commit Message

Pengxuan Zheng June 8, 2024, 3:05 a.m. UTC 
This patch is a follow-up of r15-1079-g230d62a2cdd16c to add vector floating
point trunc pattern for V2DF->V2SF and V4SF->V4HF conversions by renaming the
existing aarch64_float_truncate_lo_<mode><vczle><vczbe> pattern to the standard
optab one, i.e., trunc<Vwide><mode>2<vczle><vczbe>. This allows the vectorizer
to vectorize certain floating point narrowing operations for the aarch64 target.

gcc/ChangeLog:

	* config/aarch64/aarch64-builtins.cc (VAR1): Remap float_truncate_lo_
	builtin codes to standard optab ones.
	* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_<mode><vczle><vczbe>):
	Rename to...
	(trunc<Vwide><mode>2<vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/trunc-vec.c: New test.

Signed-off-by: Pengxuan Zheng <quic_pzheng@quicinc.com>
---
 gcc/config/aarch64/aarch64-builtins.cc       |  7 +++++++
 gcc/config/aarch64/aarch64-simd.md           |  6 +++---
 gcc/testsuite/gcc.target/aarch64/trunc-vec.c | 21 ++++++++++++++++++++
 3 files changed, 31 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/trunc-vec.c

Comments

Richard Sandiford June 10, 2024, 11:07 a.m. UTC | #1 
Pengxuan Zheng <quic_pzheng@quicinc.com> writes:
> This patch is a follow-up of r15-1079-g230d62a2cdd16c to add vector floating
> point trunc pattern for V2DF->V2SF and V4SF->V4HF conversions by renaming the
> existing aarch64_float_truncate_lo_<mode><vczle><vczbe> pattern to the standard
> optab one, i.e., trunc<Vwide><mode>2<vczle><vczbe>. This allows the vectorizer
> to vectorize certain floating point narrowing operations for the aarch64 target.
>
> gcc/ChangeLog:
>
> 	* config/aarch64/aarch64-builtins.cc (VAR1): Remap float_truncate_lo_
> 	builtin codes to standard optab ones.
> 	* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_<mode><vczle><vczbe>):
> 	Rename to...
> 	(trunc<Vwide><mode>2<vczle><vczbe>): ... This.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/aarch64/trunc-vec.c: New test.

OK, thanks.

Richard

> Signed-off-by: Pengxuan Zheng <quic_pzheng@quicinc.com>
> ---
>  gcc/config/aarch64/aarch64-builtins.cc       |  7 +++++++
>  gcc/config/aarch64/aarch64-simd.md           |  6 +++---
>  gcc/testsuite/gcc.target/aarch64/trunc-vec.c | 21 ++++++++++++++++++++
>  3 files changed, 31 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/aarch64/trunc-vec.c
>
> diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
> index 25189888d17..d589e59defc 100644
> --- a/gcc/config/aarch64/aarch64-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-builtins.cc
> @@ -543,6 +543,13 @@ BUILTIN_VDQ_BHSI (uhadd, uavg, _floor, 0)
>  VAR1 (float_extend_lo_, extend, v2sf, v2df)
>  VAR1 (float_extend_lo_, extend, v4hf, v4sf)
>  
> +/* __builtin_aarch64_float_truncate_lo_<mode> should be expanded through the
> +   standard optabs CODE_FOR_trunc<Vwide><mode>2. */
> +constexpr insn_code CODE_FOR_aarch64_float_truncate_lo_v4hf
> +    = CODE_FOR_truncv4sfv4hf2;
> +constexpr insn_code CODE_FOR_aarch64_float_truncate_lo_v2sf
> +    = CODE_FOR_truncv2dfv2sf2;
> +
>  #undef VAR1
>  #define VAR1(T, N, MAP, FLAG, A) \
>    {#N #A, UP (A), CF##MAP (N, A), 0, TYPES_##T, FLAG_##FLAG},
> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> index c5e2c9f00d0..f644bd1731e 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -3197,7 +3197,7 @@ (define_expand "aarch64_float_trunc_rodd_hi_v4sf"
>  }
>  )
>  
> -(define_insn "aarch64_float_truncate_lo_<mode><vczle><vczbe>"
> +(define_insn "trunc<Vwide><mode>2<vczle><vczbe>"
>    [(set (match_operand:VDF 0 "register_operand" "=w")
>        (float_truncate:VDF
>  	(match_operand:<VWIDE> 1 "register_operand" "w")))]
> @@ -3256,7 +3256,7 @@ (define_expand "vec_pack_trunc_v2df"
>      int lo = BYTES_BIG_ENDIAN ? 2 : 1;
>      int hi = BYTES_BIG_ENDIAN ? 1 : 2;
>  
> -    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
> +    emit_insn (gen_truncv2dfv2sf2 (tmp, operands[lo]));
>      emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
>  						   tmp, operands[hi]));
>      DONE;
> @@ -3272,7 +3272,7 @@ (define_expand "vec_pack_trunc_df"
>    {
>      rtx tmp = gen_reg_rtx (V2SFmode);
>      emit_insn (gen_aarch64_vec_concatdf (tmp, operands[1], operands[2]));
> -    emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
> +    emit_insn (gen_truncv2dfv2sf2 (operands[0], tmp));
>      DONE;
>    }
>  )
> diff --git a/gcc/testsuite/gcc.target/aarch64/trunc-vec.c b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> new file mode 100644
> index 00000000000..05e8af7912d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.2s, v[0-9]+.2d} 1 } } */
> +void
> +f (double *__restrict a, float *__restrict b)
> +{
> +  b[0] = a[0];
> +  b[1] = a[1];
> +}
> +
> +/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.4h, v[0-9]+.4s} 1 } } */
> +void
> +f1 (float *__restrict a, _Float16 *__restrict b)
> +{
> +
> +  b[0] = a[0];
> +  b[1] = a[1];
> +  b[2] = a[2];
> +  b[3] = a[3];
> +}
Pengxuan Zheng June 11, 2024, 5:01 p.m. UTC | #2 
> Pengxuan Zheng <quic_pzheng@quicinc.com> writes:
> > This patch is a follow-up of r15-1079-g230d62a2cdd16c to add vector
> > floating point trunc pattern for V2DF->V2SF and V4SF->V4HF conversions
> > by renaming the existing
> > aarch64_float_truncate_lo_<mode><vczle><vczbe> pattern to the standard
> > optab one, i.e., trunc<Vwide><mode>2<vczle><vczbe>. This allows the
> vectorizer to vectorize certain floating point narrowing operations for the
> aarch64 target.
> >
> > gcc/ChangeLog:
> >
> > 	* config/aarch64/aarch64-builtins.cc (VAR1): Remap
> float_truncate_lo_
> > 	builtin codes to standard optab ones.
> > 	* config/aarch64/aarch64-simd.md
> (aarch64_float_truncate_lo_<mode><vczle><vczbe>):
> > 	Rename to...
> > 	(trunc<Vwide><mode>2<vczle><vczbe>): ... This.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 	* gcc.target/aarch64/trunc-vec.c: New test.
> 
> OK, thanks.
> 
> Richard

Thanks, Richard! Pushed as r15-1182-ge7cd8ea1fa3e48.

Thanks,
Pengxuan
> 
> > Signed-off-by: Pengxuan Zheng <quic_pzheng@quicinc.com>
> > ---
> >  gcc/config/aarch64/aarch64-builtins.cc       |  7 +++++++
> >  gcc/config/aarch64/aarch64-simd.md           |  6 +++---
> >  gcc/testsuite/gcc.target/aarch64/trunc-vec.c | 21
> > ++++++++++++++++++++
> >  3 files changed, 31 insertions(+), 3 deletions(-)  create mode 100644
> > gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> >
> > diff --git a/gcc/config/aarch64/aarch64-builtins.cc
> > b/gcc/config/aarch64/aarch64-builtins.cc
> > index 25189888d17..d589e59defc 100644
> > --- a/gcc/config/aarch64/aarch64-builtins.cc
> > +++ b/gcc/config/aarch64/aarch64-builtins.cc
> > @@ -543,6 +543,13 @@ BUILTIN_VDQ_BHSI (uhadd, uavg, _floor, 0)
> >  VAR1 (float_extend_lo_, extend, v2sf, v2df)
> >  VAR1 (float_extend_lo_, extend, v4hf, v4sf)
> >
> > +/* __builtin_aarch64_float_truncate_lo_<mode> should be expanded
> through the
> > +   standard optabs CODE_FOR_trunc<Vwide><mode>2. */ constexpr
> > +insn_code CODE_FOR_aarch64_float_truncate_lo_v4hf
> > +    = CODE_FOR_truncv4sfv4hf2;
> > +constexpr insn_code CODE_FOR_aarch64_float_truncate_lo_v2sf
> > +    = CODE_FOR_truncv2dfv2sf2;
> > +
> >  #undef VAR1
> >  #define VAR1(T, N, MAP, FLAG, A) \
> >    {#N #A, UP (A), CF##MAP (N, A), 0, TYPES_##T, FLAG_##FLAG}, diff
> > --git a/gcc/config/aarch64/aarch64-simd.md
> > b/gcc/config/aarch64/aarch64-simd.md
> > index c5e2c9f00d0..f644bd1731e 100644
> > --- a/gcc/config/aarch64/aarch64-simd.md
> > +++ b/gcc/config/aarch64/aarch64-simd.md
> > @@ -3197,7 +3197,7 @@ (define_expand
> "aarch64_float_trunc_rodd_hi_v4sf"
> >  }
> >  )
> >
> > -(define_insn "aarch64_float_truncate_lo_<mode><vczle><vczbe>"
> > +(define_insn "trunc<Vwide><mode>2<vczle><vczbe>"
> >    [(set (match_operand:VDF 0 "register_operand" "=w")
> >        (float_truncate:VDF
> >  	(match_operand:<VWIDE> 1 "register_operand" "w")))] @@ -3256,7
> > +3256,7 @@ (define_expand "vec_pack_trunc_v2df"
> >      int lo = BYTES_BIG_ENDIAN ? 2 : 1;
> >      int hi = BYTES_BIG_ENDIAN ? 1 : 2;
> >
> > -    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
> > +    emit_insn (gen_truncv2dfv2sf2 (tmp, operands[lo]));
> >      emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
> >  						   tmp, operands[hi]));
> >      DONE;
> > @@ -3272,7 +3272,7 @@ (define_expand "vec_pack_trunc_df"
> >    {
> >      rtx tmp = gen_reg_rtx (V2SFmode);
> >      emit_insn (gen_aarch64_vec_concatdf (tmp, operands[1], operands[2]));
> > -    emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
> > +    emit_insn (gen_truncv2dfv2sf2 (operands[0], tmp));
> >      DONE;
> >    }
> >  )
> > diff --git a/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> > b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> > new file mode 100644
> > index 00000000000..05e8af7912d
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
> > @@ -0,0 +1,21 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2" } */
> > +
> > +/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.2s, v[0-9]+.2d}
> > +1 } } */ void f (double *__restrict a, float *__restrict b) {
> > +  b[0] = a[0];
> > +  b[1] = a[1];
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.4h, v[0-9]+.4s}
> > +1 } } */ void
> > +f1 (float *__restrict a, _Float16 *__restrict b) {
> > +
> > +  b[0] = a[0];
> > +  b[1] = a[1];
> > +  b[2] = a[2];
> > +  b[3] = a[3];
> > +}
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index 25189888d17..d589e59defc 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -543,6 +543,13 @@  BUILTIN_VDQ_BHSI (uhadd, uavg, _floor, 0)
 VAR1 (float_extend_lo_, extend, v2sf, v2df)
 VAR1 (float_extend_lo_, extend, v4hf, v4sf)
 
+/* __builtin_aarch64_float_truncate_lo_<mode> should be expanded through the
+   standard optabs CODE_FOR_trunc<Vwide><mode>2. */
+constexpr insn_code CODE_FOR_aarch64_float_truncate_lo_v4hf
+    = CODE_FOR_truncv4sfv4hf2;
+constexpr insn_code CODE_FOR_aarch64_float_truncate_lo_v2sf
+    = CODE_FOR_truncv2dfv2sf2;
+
 #undef VAR1
 #define VAR1(T, N, MAP, FLAG, A) \
   {#N #A, UP (A), CF##MAP (N, A), 0, TYPES_##T, FLAG_##FLAG},
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c5e2c9f00d0..f644bd1731e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3197,7 +3197,7 @@  (define_expand "aarch64_float_trunc_rodd_hi_v4sf"
 }
 )
 
-(define_insn "aarch64_float_truncate_lo_<mode><vczle><vczbe>"
+(define_insn "trunc<Vwide><mode>2<vczle><vczbe>"
   [(set (match_operand:VDF 0 "register_operand" "=w")
       (float_truncate:VDF
 	(match_operand:<VWIDE> 1 "register_operand" "w")))]
@@ -3256,7 +3256,7 @@  (define_expand "vec_pack_trunc_v2df"
     int lo = BYTES_BIG_ENDIAN ? 2 : 1;
     int hi = BYTES_BIG_ENDIAN ? 1 : 2;
 
-    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
+    emit_insn (gen_truncv2dfv2sf2 (tmp, operands[lo]));
     emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
 						   tmp, operands[hi]));
     DONE;
@@ -3272,7 +3272,7 @@  (define_expand "vec_pack_trunc_df"
   {
     rtx tmp = gen_reg_rtx (V2SFmode);
     emit_insn (gen_aarch64_vec_concatdf (tmp, operands[1], operands[2]));
-    emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
+    emit_insn (gen_truncv2dfv2sf2 (operands[0], tmp));
     DONE;
   }
 )
diff --git a/gcc/testsuite/gcc.target/aarch64/trunc-vec.c b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
new file mode 100644
index 00000000000..05e8af7912d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/trunc-vec.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.2s, v[0-9]+.2d} 1 } } */
+void
+f (double *__restrict a, float *__restrict b)
+{
+  b[0] = a[0];
+  b[1] = a[1];
+}
+
+/* { dg-final { scan-assembler-times {fcvtn\tv[0-9]+.4h, v[0-9]+.4s} 1 } } */
+void
+f1 (float *__restrict a, _Float16 *__restrict b)
+{
+
+  b[0] = a[0];
+  b[1] = a[1];
+  b[2] = a[2];
+  b[3] = a[3];
+}