diff mbox series

[RFC,v2,22/23] sysreset: rockchip: use fst reset for ARM64 SOC

Message ID 20240531141837.13189-23-linux.amoon@gmail.com
State RFC
Delegated to: Kever Yang
Headers show
Series Enable display cpuinfo to get the reset cause | expand

Commit Message

Anand Moon May 31, 2024, 2:18 p.m. UTC
From: Kever Yang <kever.yang@rock-chips.com>

Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
 drivers/sysreset/sysreset_rockchip.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Jonas Karlman May 31, 2024, 4:44 p.m. UTC | #1
Hi Anand and Kever,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Kever Yang <kever.yang@rock-chips.com>
> 
> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

What is this trying to fix? And what SoCs is affected?

My arm64 RK SoCs seem to reset using warm reset (second global reset).

> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>  drivers/sysreset/sysreset_rockchip.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
> index f353f9b4c7..17aa191349 100644
> --- a/drivers/sysreset/sysreset_rockchip.c
> +++ b/drivers/sysreset/sysreset_rockchip.c
> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
>  
>  	switch (type) {
>  	case SYSRESET_WARM:
> +#ifdef CONFIG_ARM64
> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> +#else
>  		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> +#endif

If this is needed maybe use something like this and let it fall through
to SYSRESET_COLD?

  if (!IS_ENABLED(CONFIG_ARM64)) {
	writel(0xeca8, cru_base + offset->glb_srst_snd_value);
	break;
  }

Regards,
Jonas

>  		break;
>  	case SYSRESET_COLD:
>  		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
Dragan Simic May 31, 2024, 9:55 p.m. UTC | #2
Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Kever Yang <kever.yang@rock-chips.com>
> 
> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>  drivers/sysreset/sysreset_rockchip.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/sysreset/sysreset_rockchip.c
> b/drivers/sysreset/sysreset_rockchip.c
> index f353f9b4c7..17aa191349 100644
> --- a/drivers/sysreset/sysreset_rockchip.c
> +++ b/drivers/sysreset/sysreset_rockchip.c
> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev,
> enum sysreset_t type)
> 
>  	switch (type) {
>  	case SYSRESET_WARM:
> +#ifdef CONFIG_ARM64
> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */

s/Rockchip 64bit SOC need fst reset for cpu reset entry
  /Rockchip 64-bit SoCs need FST reset for CPU reset entry/

> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> +#else
>  		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> +#endif
>  		break;
>  	case SYSRESET_COLD:
>  		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
Anand Moon June 1, 2024, 4:39 a.m. UTC | #3
Hi Jonas

On Fri, 31 May 2024 at 22:14, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Anand and Kever,
>
> On 2024-05-31 16:18, Anand Moon wrote:
> > From: Kever Yang <kever.yang@rock-chips.com>
> >
> > Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
>
> What is this trying to fix? And what SoCs is affected?
>
> My arm64 RK SoCs seem to reset using warm reset (second global reset).
>
I found this patch related to CRU so it was added in this series.
My goal is to test all the remaining SoC and see if any thing is missing
in my testing.

> >
> > Cc: Jagan Teki <jagan@edgeble.ai>
> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > ---
> >  drivers/sysreset/sysreset_rockchip.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
> > index f353f9b4c7..17aa191349 100644
> > --- a/drivers/sysreset/sysreset_rockchip.c
> > +++ b/drivers/sysreset/sysreset_rockchip.c
> > @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
> >
> >       switch (type) {
> >       case SYSRESET_WARM:
> > +#ifdef CONFIG_ARM64
> > +             /* Rockchip 64bit SOC need fst reset for cpu reset entry */
> > +             writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> > +#else
> >               writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> > +#endif
>
> If this is needed maybe use something like this and let it fall through
> to SYSRESET_COLD?
>
>   if (!IS_ENABLED(CONFIG_ARM64)) {
>         writel(0xeca8, cru_base + offset->glb_srst_snd_value);
>         break;
>   }
>

Ok I will update this in next version

> Regards,
> Jonas
Thanks
-Anand
Kever Yang July 15, 2024, 10:19 a.m. UTC | #4
On 2024/6/1 00:44, Jonas Karlman wrote:
> Hi Anand and Kever,
>
> On 2024-05-31 16:18, Anand Moon wrote:
>> From: Kever Yang <kever.yang@rock-chips.com>
>>
>> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
> What is this trying to fix? And what SoCs is affected?

Both fst and snd softreset are available for SoCs, but the fst reset 
more thing.

This commit msg is about: in some case the CPU entry may change after 
system boot,

eg. the wakeup code for deep sleep mode(which may power off) is locate 
at a different address;

with fst reset, the CPU entry is reset to the one bootRom used but the 
snd reset can not.

All the mass produced product with ARM64 SoCs are using the first global 
reset for warn reset now.


Thanks,
- Kever
> My arm64 RK SoCs seem to reset using warm reset (second global reset).
>
>> Cc: Jagan Teki <jagan@edgeble.ai>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>   drivers/sysreset/sysreset_rockchip.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
>> index f353f9b4c7..17aa191349 100644
>> --- a/drivers/sysreset/sysreset_rockchip.c
>> +++ b/drivers/sysreset/sysreset_rockchip.c
>> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
>>   
>>   	switch (type) {
>>   	case SYSRESET_WARM:
>> +#ifdef CONFIG_ARM64
>> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
>> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
>> +#else
>>   		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
>> +#endif
> If this is needed maybe use something like this and let it fall through
> to SYSRESET_COLD?
>
>    if (!IS_ENABLED(CONFIG_ARM64)) {
> 	writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> 	break;
>    }
>
> Regards,
> Jonas
>
>>   		break;
>>   	case SYSRESET_COLD:
>>   		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
diff mbox series

Patch

diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
index f353f9b4c7..17aa191349 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -22,7 +22,12 @@  int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
 
 	switch (type) {
 	case SYSRESET_WARM:
+#ifdef CONFIG_ARM64
+		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
+		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+#else
 		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+#endif
 		break;
 	case SYSRESET_COLD:
 		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);