| Message ID | 20240517145302.971019-9-cleger@rivosinc.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Add support for a few Zc* extensions, Zcmop and Zimop | expand |
On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: > +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; > +} > +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; > +} Could you write the logic in these out normally please? I think they'd be more understandable (particular this second one) broken down and with early return. Otherwise, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On 21/05/2024 21:49, Conor Dooley wrote: > On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: > >> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >> +} >> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >> +} > > Could you write the logic in these out normally please? I think they'd > be more understandable (particular this second one) broken down and with > early return. Yes sure. I'll probably make the same thing for zcf_validate as well as removing the #ifdef and using IS_ENABLED(): static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (IS_ENABLED(CONFIG_64BIT)) return -EINVAL; if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) return 0; return -EPROBE_DEFER; } > > Otherwise, > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor.
On Wed, 22 May 2024 00:20:09 PDT (-0700), cleger@rivosinc.com wrote: > > > On 21/05/2024 21:49, Conor Dooley wrote: >> On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: >> >>> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, >>> + const unsigned long *isa_bitmap) >>> +{ >>> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >>> +} >>> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, >>> + const unsigned long *isa_bitmap) >>> +{ >>> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >>> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >>> +} >> >> Could you write the logic in these out normally please? I think they'd >> be more understandable (particular this second one) broken down and with >> early return. > > Yes sure. I'll probably make the same thing for zcf_validate as well as > removing the #ifdef and using IS_ENABLED(): > > static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > if (IS_ENABLED(CONFIG_64BIT)) > return -EINVAL; > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > return 0; > > return -EPROBE_DEFER; > } Are you going to send a v6 (sorry if I missed it, I'm trying to untangle all these ISA parsing patch sets). > >> >> Otherwise, >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> >> Cheers, >> Conor.
On 30/05/2024 23:13, Palmer Dabbelt wrote: > On Wed, 22 May 2024 00:20:09 PDT (-0700), cleger@rivosinc.com wrote: >> >> >> On 21/05/2024 21:49, Conor Dooley wrote: >>> On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: >>> >>>> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data >>>> *data, >>>> + const unsigned long *isa_bitmap) >>>> +{ >>>> + return __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >>>> +} >>>> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data >>>> *data, >>>> + const unsigned long *isa_bitmap) >>>> +{ >>>> + return __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_ZCA) && >>>> + __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >>>> +} >>> >>> Could you write the logic in these out normally please? I think they'd >>> be more understandable (particular this second one) broken down and with >>> early return. >> >> Yes sure. I'll probably make the same thing for zcf_validate as well as >> removing the #ifdef and using IS_ENABLED(): >> >> static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, >> const unsigned long *isa_bitmap) >> { >> if (IS_ENABLED(CONFIG_64BIT)) >> return -EINVAL; >> >> if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) >> return 0; >> >> return -EPROBE_DEFER; >> } > > Are you going to send a v6 (sorry if I missed it, I'm trying to untangle > all these ISA parsing patch sets). Yes, I was waiting for more feedback/Rb by it seems like I now have everything I need. I'll send that. Thanks, Clément > >> >>> >>> Otherwise, >>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >>> >>> Cheers, >>> Conor.
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 1a148cd67e0e..8611e1c8ec2d 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -46,6 +46,9 @@ void riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) +#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate) + /* Used to declare pure "lasso" extension (Zk for instance) */ #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b1896dade74c..a5836fa6b998 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,10 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_ZIMOP 74 +#define RISCV_ISA_EXT_ZCA 75 +#define RISCV_ISA_EXT_ZCB 76 +#define RISCV_ISA_EXT_ZCD 77 +#define RISCV_ISA_EXT_ZCF 78 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fa4ad73b770a..3bb2ef52a38b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -103,6 +103,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, return 0; } +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; +} +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; +} + +static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ +#ifdef CONFIG_64BIT + return -EINVAL; +#else + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f) ? 0 : -EPROBE_DEFER; +#endif +} + static const unsigned int riscv_zk_bundled_exts[] = { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -183,6 +206,21 @@ static const unsigned int riscv_xlinuxenvcfg_exts[] = { RISCV_ISA_EXT_XLINUXENVCFG }; +/* + * Zc* spec states that: + * - C always implies Zca + * - C+F implies Zcf (RV32 only) + * - C+D implies Zcd + * + * These extensions will be enabled and then validated depending on the + * availability of F/D RV32. + */ +static const unsigned int riscv_c_exts[] = { + RISCV_ISA_EXT_ZCA, + RISCV_ISA_EXT_ZCF, + RISCV_ISA_EXT_ZCD, +}; + /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged specification. @@ -229,7 +267,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), - __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, @@ -248,6 +286,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), + __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), + __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/include/asm/cpufeature.h | 3 ++ arch/riscv/include/asm/hwcap.h | 4 +++ arch/riscv/kernel/cpufeature.c | 44 ++++++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-)