| Message ID | ZheoY9mZ5gAMfXWo@tucnak |
|---|---|
| State | New |
| Headers | show |
| Series | invoke.texi: Clarify -march=lujiazui | expand |
Hi Jakub: I think the modified lujiazui description is what actually happens,thanks. BR Mayshao > > > [这封邮件来自外部发件人 谨防风险] > > Hi! > > Yesterday I was searching which exact CPUs are affected by the PR114576 > wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived > at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march= > cases which do enable -maes and don't enable -mavx). > But when double-checking that against the invoke.texi documentation, > that was true for the first 3, but lujiazui said it supported AVX. > I was really confused by that, until I found the > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html > explanation. So, seems the CPUs do have AVX and F16C but -march=lujiazui > doesn't enable those and even activelly attempts to filter those out from > the announced CPUID features, in glibc as well as e.g. in libgcc. > > Thus, I think we should document what actually happens, otherwise > users could assume that > gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't. > > Tested on x86_64, ok for trunk? > > 2024-04-11 Jakub Jelinek <jakub@redhat.com> > > * doc/invoke.texi (lujiazui): Clarify that while the CPUs do support > AVX and F16C, -march=lujiazui actually doesn't enable those. > > --- gcc/doc/invoke.texi.jj 2024-04-11 09:26:01.156865894 +0200 > +++ gcc/doc/invoke.texi 2024-04-11 10:47:53.457582922 +0200 > @@ -34696,8 +34696,10 @@ instruction set support. > > @item lujiazui > ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, > -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, > -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. > +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, > +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs > +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} > +for performance reasons. > > @item yongfeng > ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, > > Jakub >
--- gcc/doc/invoke.texi.jj 2024-04-11 09:26:01.156865894 +0200 +++ gcc/doc/invoke.texi 2024-04-11 10:47:53.457582922 +0200 @@ -34696,8 +34696,10 @@ instruction set support. @item lujiazui ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} +for performance reasons. @item yongfeng ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,