| Message ID | 9UKxZxvyW2p7WWu5KwPIVoiFveSPOTEAzCVemUccLIb70r8QO7ch2PAiwVf428TC-7K9HDSO26ShohI0gnI4C671Plwa0M1CuwclJt3xJEc=@protonmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | board: starfive: support Pine64 Star64 board | expand |
Hi, On Mon, May 6, 2024 at 8:30 AM H Bell <dmoo_dv@protonmail.com> wrote: > > Similar to the Milk-V Mars, The Star64 board contains few differences to the > VisionFive 2 boards, so can be part of the same U-boot build. > > Signed-off-by: Henry Bell <dmoo_dv@protonmail.com> > Cc: ycliang@andestech.com > Cc: heinrich.schuchardt@canonical.com > --- > board/starfive/visionfive2/spl.c | 52 +++++++++++++++++++ > .../visionfive2/starfive_visionfive2.c | 4 ++ > 2 files changed, 56 insertions(+) > > diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c > index ca61b5be22..b8d29a02af 100644 > --- a/board/starfive/visionfive2/spl.c > +++ b/board/starfive/visionfive2/spl.c > @@ -226,6 +226,56 @@ void spl_fdt_fixup_version_b(void *fdt) > } > } > > +void spl_fdt_fixup_star64(void *fdt) > +{ > + static const char compat[] = "starfive,star64\0starfive,jh7110"; Should be "pine64,star64\nstarfive,jh7110" ? > + u32 phandle; > + u8 i; > + int offset; > + int ret; > + > + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); > + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", > + "Pine64 Star64"); > + > + /* gmac0 */ > + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); > + phandle = fdt_get_phandle(fdt, offset); > + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); > + > + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); > + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", > + JH7110_AONCLK_GMAC0_RMII_RTX); > + > + /* gmac1 */ > + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); > + phandle = fdt_get_phandle(fdt, offset); > + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); > + > + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); > + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", > + JH7110_SYSCLK_GMAC1_RMII_RTX); > + > + for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { > + offset = fdt_path_offset(fdt, starfive_verb[i].path); > + > + if (starfive_verb[i].value) > + ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, > + dectoul(starfive_verb[i].value, NULL)); Using the fishwaldo repo Star64_devel branch Linux sources as my reference https://github.com/Fishwaldo/Star64_linux the drive strength is 3600 and looking at StarFive repo: https://github.com/starfive-tech/u-boot/blob/223ac8b1e907924d3891b3be1b2f6620b56bff31/arch/riscv/dts/starfive_visionfive2.dts#L323 from "rgmii_sw_dr_rxc = <0x6>;" (7th enum is 3600). However the dev dts still refers to 0x7 ( i.e. " motorcomm,rx-clk-drv-microamp = <3970>;") https://github.com/starfive-tech/u-boot/blob/223ac8b1e907924d3891b3be1b2f6620b56bff31/arch/riscv/dts/starfive_devkits.dts#L289 Also the delay inverts differ somewhat. Marked-up arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dtsi from the above repo: &gmac0 { status = "okay"; #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { rgmii_sw_dr_2 = <0x0>; switch drive 1.8V operation rgmii_sw_dr = <0x3>; switch drive 4th enum is 2910 rgmii_sw_dr_rxc = <0x6>; switch clock drive rx current 7th enum is 3600 rxc_dly_en = <0>; 0 (disabled) 1900ps rxc clock additional delay added to configured rx delay (default is disabled). Default tx/rx delay value is 1950ps. rx_delay_sel = <0xa>; 1500 at 1000Mbps tx_delay_sel_fe = <5>; 750 at 10/100Mbps tx_delay_sel = <0xa>; 1500 at 1000Mbps tx_inverted_10 = <0x1>; true motorcomm,tx-clk-10-inverted tx_inverted_100 = <0x1>; true motorcomm,tx-clk-100-inverted tx_inverted_1000 = <0x1>; true motorcomm,tx-clk-1000-inverted }; }; &gmac1 { #address-cells = <1>; #size-cells = <0>; status = "okay"; phy1: ethernet-phy@1 { rgmii_sw_dr_2 = <0x0>; switch drive 2 1.8V operation rgmii_sw_dr = <0x3>; switch drive 4th enum is 2910 rgmii_sw_dr_rxc = <0x6>; switch clock drive rx current 7th enum is 3600 rxc_dly_en = <0>; 0 (disabled) 1900ps rxc clock additional delay added to configured rx delay (default is disabled). Default tx/rx delay value is 1950ps. rx_delay_sel = <0x2>; 300 at 1000Mbps tx_delay_sel_fe = <5>; 750 at 10/100Mbps tx_delay_sel = <0>; 0 at 1000Mbps tx_inverted_10 = <0x1>; motorcomm,tx-clk-10-inverted tx_inverted_100 = <0x1>; motorcomm,tx-clk-100-inverted tx_inverted_1000 = <0x0>; false (omit motorcomm,tx-clk-1000-inverted) }; }; New property names are not made clear to me how to choose these different delays for 10/100 Mbps vs 1000 Mbps operation. If the fishwaldo repo is a valid reference then it seems different than the content in starfive_vf2_pro starfive_verb[]. No Star64 here to test with, does this work as-is for both network interfaces? > + else > + ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); > + > + if (ret) { > + pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); > + break; > + } > + } > +} > + > void spl_perform_fixups(struct spl_image_info *spl_image) > { > u8 version; > @@ -252,6 +302,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) > spl_fdt_fixup_version_b(spl_image->fdt_addr); > break; > }; > + } else if (!strncmp(product_id, "STAR64", 6)) { > + spl_fdt_fixup_star64(spl_image->fdt_addr); > } else { > pr_err("Unknown product %s\n", product_id); > }; > diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c > index a86bca533b..93bc8b5c55 100644 > --- a/board/starfive/visionfive2/starfive_visionfive2.c > +++ b/board/starfive/visionfive2/starfive_visionfive2.c > @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; > "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" > #define FDTFILE_VISIONFIVE2_1_3B \ > "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" > +#define FDTFILE_PINE64_STAR64 \ > + "starfive/pine64-star64.dtb" Should be "starfive/jh7110-pine64-star64.dtb" ? > > /* enable U74-mc hart1~hart4 prefetcher */ > static void enable_prefetcher(void) > @@ -78,6 +80,8 @@ static void set_fdtfile(void) > fdtfile = FDTFILE_VISIONFIVE2_1_3B; > break; > } > + } else if (!strncmp(product_id, "STAR64", 6)) { > + fdtfile = FDTFILE_PINE64_STAR64; > } else { > log_err("Unknown product\n"); > return; > -- > 2.44.0 > Best regards, -E
On Tuesday, May 7th, 2024 at 12:31 AM, E Shattow <lucent@gmail.com> wrote: > On Mon, May 6, 2024 at 8:30 AM H Bell <dmoo_dv@protonmail.com> wrote: > > + static const char compat[] = "starfive,star64\0starfive,jh7110"; > Should be "pine64,star64\nstarfive,jh7110" ? changed to "pine64,star64\0starfive,jh7110" in v2 On Tuesday, May 7th, 2024 at 12:31 AM, E Shattow <lucent@gmail.com> wrote: > New property names are not made clear to me how to choose these > different delays for 10/100 Mbps vs 1000 Mbps operation. If the > fishwaldo repo is a valid reference then it seems different than the > content in starfive_vf2_pro starfive_verb[]. No Star64 here to test > with, does this work as-is for both network interfaces? Agreed. I've created a separate object in v2 for some further investigations with the delays/timings to make sure they're both working On Tuesday, May 7th, 2024 at 12:31 AM, E Shattow <lucent@gmail.com> wrote: > On Mon, May 6, 2024 at 8:30 AM H Bell <dmoo_dv@protonmail.com> wrote: > > +#define FDTFILE_PINE64_STAR64 \ > > + "starfive/pine64-star64.dtb" > Should be "starfive/jh7110-pine64-star64.dtb" ? fixed in v2
On Pine64 Star64 8GB (May 2023 order date: "Star64 v1.1" silkscreen) by contributor Tenkawa (contact info withheld so posting on their behalf and listing myself in the tag). Other than the inconclusive networking result (for discussion via code review) it seems to have basic functionality. # mac Vendor : PINE64 Product full SN: STAR64V1-2310-D008E000-00000005 data version: 0x2 PCB revision: 0xc1 BOM revision: A Ethernet MAC0 address: 6c:cf:39:00:75:61 Ethernet MAC1 address: 6c:cf:39:00:75:62 # mmc info Device: mmc@16010000 Manufacturer ID: 15 OEM: 0 Name: BJTD4R Bus Speed: 52000000 Mode: MMC High Speed (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 29.1 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 29.1 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected # mmc dev 1 ; mmc info switch to partitions #0, OK mmc1 is current device Device: mmc@16020000 Manufacturer ID: 1b OEM: 534d Name: GD2S5 Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 119.4 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes # # Silkscreen: Upper=A Port # env erase;env load;env set bootcmd 'dhcp;net list'; env save; reset ethernet@16030000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! phy_startup() failed: -110 FAILED: -110 ethernet@16040000 Waiting for PHY auto negotiation to complete....... done BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address... ... eth0 : ethernet@16030000 6c:cf:39:00:75:61 active eth1 : ethernet@16040000 6c:cf:39:00:75:62 # # Silkscreen: Lower=B Port # env erase;env load;env set bootcmd 'dhcp;net list'; env save; reset ethernet@16030000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! phy_startup() failed: -110 FAILED: -110 ethernet@16040000 Waiting for PHY auto negotiation to complete....... done BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address... ... eth0 : ethernet@16030000 6c:cf:39:00:75:61 eth1 : ethernet@16040000 6c:cf:39:00:75:62 active Some dropped network packets were observed with the test setup: Approx 6% packet loss on Upper=A Port Approx 71% packet loss on Lower=B Port. The test network was not known to be reliable and might have introduced other sources of error. No comparison was available to any other firmware releases. Tested-by: E Shattow <lucent@gmail.com> On Mon, May 6, 2024 at 8:30 AM H Bell <dmoo_dv@protonmail.com> wrote: > > Similar to the Milk-V Mars, The Star64 board contains few differences to the > VisionFive 2 boards, so can be part of the same U-boot build. > > Signed-off-by: Henry Bell <dmoo_dv@protonmail.com> > Cc: ycliang@andestech.com > Cc: heinrich.schuchardt@canonical.com > --- > board/starfive/visionfive2/spl.c | 52 +++++++++++++++++++ > .../visionfive2/starfive_visionfive2.c | 4 ++ > 2 files changed, 56 insertions(+) > > diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c > index ca61b5be22..b8d29a02af 100644 > --- a/board/starfive/visionfive2/spl.c > +++ b/board/starfive/visionfive2/spl.c > @@ -226,6 +226,56 @@ void spl_fdt_fixup_version_b(void *fdt) > } > } > > +void spl_fdt_fixup_star64(void *fdt) > +{ > + static const char compat[] = "starfive,star64\0starfive,jh7110"; > + u32 phandle; > + u8 i; > + int offset; > + int ret; > + > + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); > + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", > + "Pine64 Star64"); > + > + /* gmac0 */ > + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); > + phandle = fdt_get_phandle(fdt, offset); > + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); > + > + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); > + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", > + JH7110_AONCLK_GMAC0_RMII_RTX); > + > + /* gmac1 */ > + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); > + phandle = fdt_get_phandle(fdt, offset); > + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); > + > + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); > + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); > + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", > + JH7110_SYSCLK_GMAC1_RMII_RTX); > + > + for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { > + offset = fdt_path_offset(fdt, starfive_verb[i].path); > + > + if (starfive_verb[i].value) > + ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, > + dectoul(starfive_verb[i].value, NULL)); > + else > + ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); > + > + if (ret) { > + pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); > + break; > + } > + } > +} > + > void spl_perform_fixups(struct spl_image_info *spl_image) > { > u8 version; > @@ -252,6 +302,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) > spl_fdt_fixup_version_b(spl_image->fdt_addr); > break; > }; > + } else if (!strncmp(product_id, "STAR64", 6)) { > + spl_fdt_fixup_star64(spl_image->fdt_addr); > } else { > pr_err("Unknown product %s\n", product_id); > }; > diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c > index a86bca533b..93bc8b5c55 100644 > --- a/board/starfive/visionfive2/starfive_visionfive2.c > +++ b/board/starfive/visionfive2/starfive_visionfive2.c > @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; > "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" > #define FDTFILE_VISIONFIVE2_1_3B \ > "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" > +#define FDTFILE_PINE64_STAR64 \ > + "starfive/pine64-star64.dtb" > > /* enable U74-mc hart1~hart4 prefetcher */ > static void enable_prefetcher(void) > @@ -78,6 +80,8 @@ static void set_fdtfile(void) > fdtfile = FDTFILE_VISIONFIVE2_1_3B; > break; > } > + } else if (!strncmp(product_id, "STAR64", 6)) { > + fdtfile = FDTFILE_PINE64_STAR64; > } else { > log_err("Unknown product\n"); > return; > -- > 2.44.0 >
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index ca61b5be22..b8d29a02af 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -226,6 +226,56 @@ void spl_fdt_fixup_version_b(void *fdt) } } +void spl_fdt_fixup_star64(void *fdt) +{ + static const char compat[] = "starfive,star64\0starfive,jh7110"; + u32 phandle; + u8 i; + int offset; + int ret; + + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", + "Pine64 Star64"); + + /* gmac0 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_AONCLK_GMAC0_RMII_RTX); + + /* gmac1 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_SYSCLK_GMAC1_RMII_RTX); + + for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { + offset = fdt_path_offset(fdt, starfive_verb[i].path); + + if (starfive_verb[i].value) + ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, + dectoul(starfive_verb[i].value, NULL)); + else + ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); + + if (ret) { + pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); + break; + } + } +} + void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; @@ -252,6 +302,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) spl_fdt_fixup_version_b(spl_image->fdt_addr); break; }; + } else if (!strncmp(product_id, "STAR64", 6)) { + spl_fdt_fixup_star64(spl_image->fdt_addr); } else { pr_err("Unknown product %s\n", product_id); }; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index a86bca533b..93bc8b5c55 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" +#define FDTFILE_PINE64_STAR64 \ + "starfive/pine64-star64.dtb" /* enable U74-mc hart1~hart4 prefetcher */ static void enable_prefetcher(void) @@ -78,6 +80,8 @@ static void set_fdtfile(void) fdtfile = FDTFILE_VISIONFIVE2_1_3B; break; } + } else if (!strncmp(product_id, "STAR64", 6)) { + fdtfile = FDTFILE_PINE64_STAR64; } else { log_err("Unknown product\n"); return;
Similar to the Milk-V Mars, The Star64 board contains few differences to the VisionFive 2 boards, so can be part of the same U-boot build. Signed-off-by: Henry Bell <dmoo_dv@protonmail.com> Cc: ycliang@andestech.com Cc: heinrich.schuchardt@canonical.com --- board/starfive/visionfive2/spl.c | 52 +++++++++++++++++++ .../visionfive2/starfive_visionfive2.c | 4 ++ 2 files changed, 56 insertions(+)