| Message ID | 20240420044901.884098-1-quic_kriskura@quicinc.com |
|---|---|
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
> > Currently the DWC3 driver supports only single port controller which requires at > most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS mode. > > This change primarily refactors the Phy logic in core driver to allow multiport > support with Generic Phy's. > > The DWC3 controller supports up to 15 High-Speed phys and 4 SuperSpeed phys. > The multiport controller in Qualcomm SA8295P is paired with two High-Speed + > SuperSpeed and two High-Speed-only ports. It is assumed that the N > SuperSpeed PHYs are paired with the first N High-Speed PHYs. > Hi All, Thinh Can DW multiple port host patches be (patch 1-4) accepted first? Other multiport vendor will use this.
On Sat, Apr 20, 2024 at 10:18:54AM +0530, Krishna Kurapati wrote: > All DWC3 Multi Port controllers that exist today only support host mode. > Temporarily map XHCI address space for host-only controllers and parse > XHCI Extended Capabilities registers to read number of usb2 ports and > usb3 ports present on multiport controller. Each USB Port is at least HS > capable. > > The port info for usb2 and usb3 phy are identified as num_usb2_ports > and num_usb3_ports and these are used as iterators for phy operations > and for modifying GUSB2PHYCFG/ GUSB3PIPECTL registers accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Sat, Apr 20, 2024 at 10:18:56AM +0530, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller > which requires at least one HS PHY and at most one SS PHY. > > But the DWC3 USB controller can be connected to multiple ports and > each port can have their own PHYs. Each port of the multiport > controller can either be HS+SS capable or HS only capable > Proper quantification of them is required to modify GUSB2PHYCFG > and GUSB3PIPECTL registers appropriately. > > DWC3 multiport controllers are capable to service at most 15 High Speed > PHYs and 4 Supser Speed PHYs. Add support for detecting, obtaining and > configuring PHYs supported by a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Sat, Apr 20, 2024 at 10:18:58AM +0530, Krishna Kurapati wrote: > The logic for requesting interrupts is duplicated for each interrupt. In > the upcoming patches that introduces support for multiport, it would be > better to clean up the duplication before reading mulitport related > interrupts. > > Refactor interrupt setup call by adding a new helper function for > requesting the wakeup interrupts. To simplify implementation, make > the display name same as the interrupt name expected in Device tree. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> As far I can see, you only replaced "DT" with "Device tree" in the commit message. For changes like that you could have kept my Reviewed-by tag (but I appreciate that you dropped it from some of the others): Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Sat, Apr 20, 2024 at 10:18:59AM +0530, Krishna Kurapati wrote: > On multiport supported controllers, each port has its own DP/DM and > SuperSpeed (if super speed capable) interrupts. As per the bindings, > their interrupt names differ from single-port ones by having a "_x" > added as suffix (x being the port number). Identify from the interrupt > names whether the controller is a multiport controller or not. > Refactor dwc3_qcom_setup_irq() call to parse multiportinterrupts along > with non-multiport ones accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Sat, Apr 20, 2024 at 10:19:01AM +0530, Krishna Kurapati wrote: > Power event IRQ is used for wakeup either when the controller is > SuperSpeed capable but is missing an SuperSpeed PHY interrupt, or when > the GIC is not capable of detecting DP/DM High-Speed PHY interrupts. > > The Power event IRQ stat register indicates whether the High-Speed > phy entered and exited L2 successfully during suspend and resume. > Indicate the same for all ports of a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Mon, Apr 22, 2024 at 01:21:07AM +0000, Minda Chen wrote: > Can DW multiple port host patches be (patch 1-4) accepted first? > Other multiport vendor will use this. The whole series is good to go and should be merged for 6.10 so there's no need to split things up. Johan
On Sat, Apr 20, 2024 at 10:18:52AM +0530, Krishna Kurapati wrote: > Krishna Kurapati (9): > dt-bindings: usb: Add bindings for multiport properties on DWC3 > controller > usb: dwc3: core: Access XHCI address space temporarily to read port > info > usb: dwc3: core: Skip setting event buffers for host only controllers > usb: dwc3: core: Refactor PHY logic to support Multiport Controller > dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport > usb: dwc3: qcom: Add helper function to request wakeup interrupts > usb: dwc3: qcom: Refactor IRQ handling in glue driver > usb: dwc3: qcom: Enable wakeup for applicable ports of multiport > usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Verified that the finger print reader on the Lenovo ThinkPad X13s works with this series (and not yet merged devicetree changes). Not sure when or why, but the error message I previously reported seeing during suspend is now also gone: dwc3-qcom a4f8800.usb: HS-PHY2 not in L2 Tested-by: Johan Hovold <johan+linaro@kernel.org> Thanks for sticking with it, Krishna. Johan
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > All DWC3 Multi Port controllers that exist today only support host mode. > Temporarily map XHCI address space for host-only controllers and parse > XHCI Extended Capabilities registers to read number of usb2 ports and > usb3 ports present on multiport controller. Each USB Port is at least HS > capable. > > The port info for usb2 and usb3 phy are identified as num_usb2_ports > and num_usb3_ports and these are used as iterators for phy operations > and for modifying GUSB2PHYCFG/ GUSB3PIPECTL registers accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++ > drivers/usb/dwc3/core.h | 5 ++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 637194af506f..38fcf530332f 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -39,6 +39,7 @@ > #include "io.h" > > #include "debug.h" > +#include "../host/xhci-ext-caps.h" > > #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ > > @@ -1884,10 +1885,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc) > return 0; > } > > +static int dwc3_get_num_ports(struct dwc3 *dwc) > +{ > + void __iomem *base; > + u8 major_revision; > + u32 offset; > + u32 val; > + > + /* > + * Remap xHCI address space to access XHCI ext cap regs since it is > + * needed to get information on number of ports present. > + */ > + base = ioremap(dwc->xhci_resources[0].start, > + resource_size(&dwc->xhci_resources[0])); > + if (!base) > + return -ENOMEM; > + > + offset = 0; > + do { > + offset = xhci_find_next_ext_cap(base, offset, > + XHCI_EXT_CAPS_PROTOCOL); > + if (!offset) > + break; > + > + val = readl(base + offset); > + major_revision = XHCI_EXT_PORT_MAJOR(val); > + > + val = readl(base + offset + 0x08); > + if (major_revision == 0x03) { > + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); > + } else if (major_revision <= 0x02) { > + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); > + } else { > + dev_warn(dwc->dev, "unrecognized port major revision %d\n", > + major_revision); > + } > + } while (1); > + > + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", > + dwc->num_usb2_ports, dwc->num_usb3_ports); > + > + iounmap(base); > + > + return 0; > +} > + > static int dwc3_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct resource *res, dwc_res; > + unsigned int hw_mode; > void __iomem *regs; > struct dwc3 *dwc; > int ret; > @@ -1971,6 +2018,20 @@ static int dwc3_probe(struct platform_device *pdev) > goto err_disable_clks; > } > > + /* > + * Currently only DWC3 controllers that are host-only capable > + * can have more than one port. > + */ > + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); > + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { > + ret = dwc3_get_num_ports(dwc); > + if (ret) > + goto err_disable_clks; > + } else { > + dwc->num_usb2_ports = 1; > + dwc->num_usb3_ports = 1; > + } > + > spin_lock_init(&dwc->lock); > mutex_init(&dwc->mutex); > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 7e80dd3d466b..341e4c73cb2e 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -1039,6 +1039,8 @@ struct dwc3_scratchpad_array { > * @usb3_phy: pointer to USB3 PHY > * @usb2_generic_phy: pointer to USB2 PHY > * @usb3_generic_phy: pointer to USB3 PHY > + * @num_usb2_ports: number of USB2 ports > + * @num_usb3_ports: number of USB3 ports > * @phys_ready: flag to indicate that PHYs are ready > * @ulpi: pointer to ulpi interface > * @ulpi_ready: flag to indicate that ULPI is initialized > @@ -1187,6 +1189,9 @@ struct dwc3 { > struct phy *usb2_generic_phy; > struct phy *usb3_generic_phy; > > + u8 num_usb2_ports; > + u8 num_usb3_ports; > + > bool phys_ready; > > struct ulpi *ulpi; > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller > which requires at least one HS PHY and at most one SS PHY. > > But the DWC3 USB controller can be connected to multiple ports and > each port can have their own PHYs. Each port of the multiport > controller can either be HS+SS capable or HS only capable > Proper quantification of them is required to modify GUSB2PHYCFG > and GUSB3PIPECTL registers appropriately. > > DWC3 multiport controllers are capable to service at most 15 High Speed > PHYs and 4 Supser Speed PHYs. Add support for detecting, obtaining and > configuring PHYs supported by a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/core.c | 255 ++++++++++++++++++++++++++++------------ > drivers/usb/dwc3/core.h | 15 ++- > drivers/usb/dwc3/drd.c | 15 ++- > 3 files changed, 201 insertions(+), 84 deletions(-) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 733b1e24af54..4dc6fc79c6d9 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work) > int ret; > u32 reg; > u32 desired_dr_role; > + int i; > > mutex_lock(&dwc->mutex); > spin_lock_irqsave(&dwc->lock, flags); > @@ -201,8 +202,12 @@ static void __dwc3_set_mode(struct work_struct *work) > } else { > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, true); > - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); > - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); > + > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); > + > if (dwc->dis_split_quirk) { > reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); > reg |= DWC3_GUCTL3_SPLITDISABLE; > @@ -217,8 +222,8 @@ static void __dwc3_set_mode(struct work_struct *work) > > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, false); > - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); > - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); > + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); > + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); > > ret = dwc3_gadget_init(dwc); > if (ret) > @@ -589,22 +594,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc) > return ret; > } > > -/** > - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core > - * @dwc: Pointer to our controller context structure > - * > - * Returns 0 on success. The USB PHY interfaces are configured but not > - * initialized. The PHY interfaces and the PHYs get initialized together with > - * the core in dwc3_core_init. > - */ > -static int dwc3_phy_setup(struct dwc3 *dwc) > +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) > { > unsigned int hw_mode; > u32 reg; > > hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); > > - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); > + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); > > /* > * Make sure UX_EXIT_PX is cleared as that causes issues with some > @@ -659,9 +656,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc) > if (dwc->dis_del_phy_power_chg_quirk) > reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; > > - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); > + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); > + > + return 0; > +} > + > +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) > +{ > + unsigned int hw_mode; > + u32 reg; > > - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); > + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); > + > + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); > > /* Select the HS PHY interface */ > switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { > @@ -673,7 +680,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc) > } else if (dwc->hsphy_interface && > !strncmp(dwc->hsphy_interface, "ulpi", 4)) { > reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; > - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); > } else { > /* Relying on default value. */ > if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) > @@ -740,7 +747,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc) > if (dwc->ulpi_ext_vbus_drv) > reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; > > - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); > + > + return 0; > +} > + > +/** > + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core > + * @dwc: Pointer to our controller context structure > + * > + * Returns 0 on success. The USB PHY interfaces are configured but not > + * initialized. The PHY interfaces and the PHYs get initialized together with > + * the core in dwc3_core_init. > + */ > +static int dwc3_phy_setup(struct dwc3 *dwc) > +{ > + int i; > + int ret; > + > + for (i = 0; i < dwc->num_usb3_ports; i++) { > + ret = dwc3_ss_phy_setup(dwc, i); > + if (ret) > + return ret; > + } > + > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + ret = dwc3_hs_phy_setup(dwc, i); > + if (ret) > + return ret; > + } > > return 0; > } > @@ -748,23 +783,34 @@ static int dwc3_phy_setup(struct dwc3 *dwc) > static int dwc3_phy_init(struct dwc3 *dwc) > { > int ret; > + int i; > + int j; > > usb_phy_init(dwc->usb2_phy); > usb_phy_init(dwc->usb3_phy); > > - ret = phy_init(dwc->usb2_generic_phy); > - if (ret < 0) > - goto err_shutdown_usb3_phy; > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + ret = phy_init(dwc->usb2_generic_phy[i]); > + if (ret < 0) > + goto err_exit_usb2_phy; > + } > > - ret = phy_init(dwc->usb3_generic_phy); > - if (ret < 0) > - goto err_exit_usb2_phy; > + for (j = 0; j < dwc->num_usb3_ports; j++) { > + ret = phy_init(dwc->usb3_generic_phy[j]); > + if (ret < 0) > + goto err_exit_usb3_phy; > + } > > return 0; > > +err_exit_usb3_phy: > + while (--j >= 0) > + phy_exit(dwc->usb3_generic_phy[j]); > + > err_exit_usb2_phy: > - phy_exit(dwc->usb2_generic_phy); > -err_shutdown_usb3_phy: > + while (--i >= 0) > + phy_exit(dwc->usb2_generic_phy[i]); > + > usb_phy_shutdown(dwc->usb3_phy); > usb_phy_shutdown(dwc->usb2_phy); > > @@ -773,8 +819,13 @@ static int dwc3_phy_init(struct dwc3 *dwc) > > static void dwc3_phy_exit(struct dwc3 *dwc) > { > - phy_exit(dwc->usb3_generic_phy); > - phy_exit(dwc->usb2_generic_phy); > + int i; > + > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_exit(dwc->usb3_generic_phy[i]); > + > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_exit(dwc->usb2_generic_phy[i]); > > usb_phy_shutdown(dwc->usb3_phy); > usb_phy_shutdown(dwc->usb2_phy); > @@ -783,23 +834,34 @@ static void dwc3_phy_exit(struct dwc3 *dwc) > static int dwc3_phy_power_on(struct dwc3 *dwc) > { > int ret; > + int i; > + int j; > > usb_phy_set_suspend(dwc->usb2_phy, 0); > usb_phy_set_suspend(dwc->usb3_phy, 0); > > - ret = phy_power_on(dwc->usb2_generic_phy); > - if (ret < 0) > - goto err_suspend_usb3_phy; > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + ret = phy_power_on(dwc->usb2_generic_phy[i]); > + if (ret < 0) > + goto err_power_off_usb2_phy; > + } > > - ret = phy_power_on(dwc->usb3_generic_phy); > - if (ret < 0) > - goto err_power_off_usb2_phy; > + for (j = 0; j < dwc->num_usb3_ports; j++) { > + ret = phy_power_on(dwc->usb3_generic_phy[j]); > + if (ret < 0) > + goto err_power_off_usb3_phy; > + } > > return 0; > > +err_power_off_usb3_phy: > + while (--j >= 0) > + phy_power_off(dwc->usb3_generic_phy[j]); > + > err_power_off_usb2_phy: > - phy_power_off(dwc->usb2_generic_phy); > -err_suspend_usb3_phy: > + while (--i >= 0) > + phy_power_off(dwc->usb2_generic_phy[i]); > + > usb_phy_set_suspend(dwc->usb3_phy, 1); > usb_phy_set_suspend(dwc->usb2_phy, 1); > > @@ -808,8 +870,13 @@ static int dwc3_phy_power_on(struct dwc3 *dwc) > > static void dwc3_phy_power_off(struct dwc3 *dwc) > { > - phy_power_off(dwc->usb3_generic_phy); > - phy_power_off(dwc->usb2_generic_phy); > + int i; > + > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_power_off(dwc->usb3_generic_phy[i]); > + > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_power_off(dwc->usb2_generic_phy[i]); > > usb_phy_set_suspend(dwc->usb3_phy, 1); > usb_phy_set_suspend(dwc->usb2_phy, 1); > @@ -1201,6 +1268,7 @@ static int dwc3_core_init(struct dwc3 *dwc) > unsigned int hw_mode; > u32 reg; > int ret; > + int i; > > hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); > > @@ -1244,15 +1312,19 @@ static int dwc3_core_init(struct dwc3 *dwc) > if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && > !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { > if (!dwc->dis_u3_susphy_quirk) { > - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); > - reg |= DWC3_GUSB3PIPECTL_SUSPHY; > - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); > + for (i = 0; i < dwc->num_usb3_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); > + reg |= DWC3_GUSB3PIPECTL_SUSPHY; > + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); > + } > } > > if (!dwc->dis_u2_susphy_quirk) { > - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); > - reg |= DWC3_GUSB2PHYCFG_SUSPHY; > - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); > + reg |= DWC3_GUSB2PHYCFG_SUSPHY; > + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); > + } > } > } > > @@ -1375,7 +1447,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc) > { > struct device *dev = dwc->dev; > struct device_node *node = dev->of_node; > + char phy_name[9]; > int ret; > + int i; > > if (node) { > dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); > @@ -1401,22 +1475,38 @@ static int dwc3_core_get_phy(struct dwc3 *dwc) > return dev_err_probe(dev, ret, "no usb3 phy configured\n"); > } > > - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); > - if (IS_ERR(dwc->usb2_generic_phy)) { > - ret = PTR_ERR(dwc->usb2_generic_phy); > - if (ret == -ENOSYS || ret == -ENODEV) > - dwc->usb2_generic_phy = NULL; > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + if (dwc->num_usb2_ports == 1) > + snprintf(phy_name, sizeof(phy_name), "usb2-phy"); > else > - return dev_err_probe(dev, ret, "no usb2 phy configured\n"); > + snprintf(phy_name, sizeof(phy_name), "usb2-%d", i); > + > + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); > + if (IS_ERR(dwc->usb2_generic_phy[i])) { > + ret = PTR_ERR(dwc->usb2_generic_phy[i]); > + if (ret == -ENOSYS || ret == -ENODEV) > + dwc->usb2_generic_phy[i] = NULL; > + else > + return dev_err_probe(dev, ret, "failed to lookup phy %s\n", > + phy_name); > + } > } > > - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); > - if (IS_ERR(dwc->usb3_generic_phy)) { > - ret = PTR_ERR(dwc->usb3_generic_phy); > - if (ret == -ENOSYS || ret == -ENODEV) > - dwc->usb3_generic_phy = NULL; > + for (i = 0; i < dwc->num_usb3_ports; i++) { > + if (dwc->num_usb3_ports == 1) > + snprintf(phy_name, sizeof(phy_name), "usb3-phy"); > else > - return dev_err_probe(dev, ret, "no usb3 phy configured\n"); > + snprintf(phy_name, sizeof(phy_name), "usb3-%d", i); > + > + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); > + if (IS_ERR(dwc->usb3_generic_phy[i])) { > + ret = PTR_ERR(dwc->usb3_generic_phy[i]); > + if (ret == -ENOSYS || ret == -ENODEV) > + dwc->usb3_generic_phy[i] = NULL; > + else > + return dev_err_probe(dev, ret, "failed to lookup phy %s\n", > + phy_name); > + } > } > > return 0; > @@ -1426,6 +1516,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) > { > struct device *dev = dwc->dev; > int ret; > + int i; > > switch (dwc->dr_mode) { > case USB_DR_MODE_PERIPHERAL: > @@ -1433,8 +1524,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) > > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, false); > - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); > - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); > + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); > + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); > > ret = dwc3_gadget_init(dwc); > if (ret) > @@ -1445,8 +1536,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) > > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, true); > - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); > - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); > > ret = dwc3_host_init(dwc); > if (ret) > @@ -1940,6 +2033,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc) > > iounmap(base); > > + if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || > + dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) > + return -EINVAL; > + > return 0; > } > > @@ -2177,6 +2274,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) > { > unsigned long flags; > u32 reg; > + int i; > > switch (dwc->current_dr_role) { > case DWC3_GCTL_PRTCAP_DEVICE: > @@ -2195,17 +2293,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) > /* Let controller to suspend HSPHY before PHY driver suspends */ > if (dwc->dis_u2_susphy_quirk || > dwc->dis_enblslpm_quirk) { > - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); > - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | > - DWC3_GUSB2PHYCFG_SUSPHY; > - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); > + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | > + DWC3_GUSB2PHYCFG_SUSPHY; > + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); > + } > > /* Give some time for USB2 PHY to suspend */ > usleep_range(5000, 6000); > } > > - phy_pm_runtime_put_sync(dwc->usb2_generic_phy); > - phy_pm_runtime_put_sync(dwc->usb3_generic_phy); > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); > break; > case DWC3_GCTL_PRTCAP_OTG: > /* do nothing during runtime_suspend */ > @@ -2235,6 +2337,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) > unsigned long flags; > int ret; > u32 reg; > + int i; > > switch (dwc->current_dr_role) { > case DWC3_GCTL_PRTCAP_DEVICE: > @@ -2254,17 +2357,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) > break; > } > /* Restore GUSB2PHYCFG bits that were modified in suspend */ > - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); > - if (dwc->dis_u2_susphy_quirk) > - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); > + if (dwc->dis_u2_susphy_quirk) > + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; > > - if (dwc->dis_enblslpm_quirk) > - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; > + if (dwc->dis_enblslpm_quirk) > + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; > > - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); > + } > > - phy_pm_runtime_get_sync(dwc->usb2_generic_phy); > - phy_pm_runtime_get_sync(dwc->usb3_generic_phy); > + for (i = 0; i < dwc->num_usb2_ports; i++) > + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); > + for (i = 0; i < dwc->num_usb3_ports; i++) > + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); > break; > case DWC3_GCTL_PRTCAP_OTG: > /* nothing to do on runtime_resume */ > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 341e4c73cb2e..5cbc64883dbc 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -33,6 +33,13 @@ > > #include <linux/power_supply.h> > > +/* > + * DWC3 Multiport controllers support up to 15 High-Speed PHYs > + * and 4 SuperSpeed PHYs. > + */ > +#define DWC3_USB2_MAX_PORTS 15 > +#define DWC3_USB3_MAX_PORTS 4 > + > #define DWC3_MSG_MAX 500 > > /* Global constants */ > @@ -1037,8 +1044,8 @@ struct dwc3_scratchpad_array { > * @usb_psy: pointer to power supply interface. > * @usb2_phy: pointer to USB2 PHY > * @usb3_phy: pointer to USB3 PHY > - * @usb2_generic_phy: pointer to USB2 PHY > - * @usb3_generic_phy: pointer to USB3 PHY > + * @usb2_generic_phy: pointer to array of USB2 PHYs > + * @usb3_generic_phy: pointer to array of USB3 PHYs > * @num_usb2_ports: number of USB2 ports > * @num_usb3_ports: number of USB3 ports > * @phys_ready: flag to indicate that PHYs are ready > @@ -1186,8 +1193,8 @@ struct dwc3 { > struct usb_phy *usb2_phy; > struct usb_phy *usb3_phy; > > - struct phy *usb2_generic_phy; > - struct phy *usb3_generic_phy; > + struct phy *usb2_generic_phy[DWC3_USB2_MAX_PORTS]; > + struct phy *usb3_generic_phy[DWC3_USB3_MAX_PORTS]; > > u8 num_usb2_ports; > u8 num_usb3_ports; > diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c > index 57ddd2e43022..d76ae676783c 100644 > --- a/drivers/usb/dwc3/drd.c > +++ b/drivers/usb/dwc3/drd.c > @@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) > u32 reg; > int id; > unsigned long flags; > + int i; > > if (dwc->dr_mode != USB_DR_MODE_OTG) > return; > @@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) > } else { > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, true); > - if (dwc->usb2_generic_phy) > - phy_set_mode(dwc->usb2_generic_phy, > - PHY_MODE_USB_HOST); > + for (i = 0; i < dwc->num_usb2_ports; i++) { > + if (dwc->usb2_generic_phy[i]) { > + phy_set_mode(dwc->usb2_generic_phy[i], > + PHY_MODE_USB_HOST); > + } > + } > } > break; > case DWC3_OTG_ROLE_DEVICE: > @@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) > > if (dwc->usb2_phy) > otg_set_vbus(dwc->usb2_phy->otg, false); > - if (dwc->usb2_generic_phy) > - phy_set_mode(dwc->usb2_generic_phy, > - PHY_MODE_USB_DEVICE); > + if (dwc->usb2_generic_phy[0]) > + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); > ret = dwc3_gadget_init(dwc); > if (ret) > dev_err(dwc->dev, "failed to initialize peripheral\n"); > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > The logic for requesting interrupts is duplicated for each interrupt. In > the upcoming patches that introduces support for multiport, it would be > better to clean up the duplication before reading mulitport related > interrupts. > > Refactor interrupt setup call by adding a new helper function for > requesting the wakeup interrupts. To simplify implementation, make > the display name same as the interrupt name expected in Device tree. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/dwc3-qcom.c | 53 ++++++++++++++++-------------------- > 1 file changed, 24 insertions(+), 29 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index f6b2fab49d5e..cae5dab8fcfc 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -501,6 +501,22 @@ static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) > PIPE_UTMI_CLK_DIS); > } > > +static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, > + const char *name) > +{ > + int ret; > + > + /* Keep wakeup interrupts disabled until suspend */ > + ret = devm_request_threaded_irq(qcom->dev, irq, NULL, > + qcom_dwc3_resume_irq, > + IRQF_ONESHOT | IRQF_NO_AUTOEN, > + name, qcom); > + if (ret) > + dev_err(qcom->dev, "failed to request irq %s: %d\n", name, ret); > + > + return ret; > +} > + > static int dwc3_qcom_setup_irq(struct platform_device *pdev) > { > struct dwc3_qcom *qcom = platform_get_drvdata(pdev); > @@ -509,54 +525,33 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev) > > irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); > if (irq > 0) { > - /* Keep wakeup interrupts disabled until suspend */ > - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, > - qcom_dwc3_resume_irq, > - IRQF_ONESHOT | IRQF_NO_AUTOEN, > - "qcom_dwc3 QUSB2", qcom); > - if (ret) { > - dev_err(qcom->dev, "qusb2_phy_irq failed: %d\n", ret); > + ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); > + if (ret) > return ret; > - } > qcom->qusb2_phy_irq = irq; > } > > irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_irq"); > if (irq > 0) { > - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, > - qcom_dwc3_resume_irq, > - IRQF_ONESHOT | IRQF_NO_AUTOEN, > - "qcom_dwc3 DP_HS", qcom); > - if (ret) { > - dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); > + ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq"); > + if (ret) > return ret; > - } > qcom->dp_hs_phy_irq = irq; > } > > irq = platform_get_irq_byname_optional(pdev, "dm_hs_phy_irq"); > if (irq > 0) { > - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, > - qcom_dwc3_resume_irq, > - IRQF_ONESHOT | IRQF_NO_AUTOEN, > - "qcom_dwc3 DM_HS", qcom); > - if (ret) { > - dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); > + ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq"); > + if (ret) > return ret; > - } > qcom->dm_hs_phy_irq = irq; > } > > irq = platform_get_irq_byname_optional(pdev, "ss_phy_irq"); > if (irq > 0) { > - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, > - qcom_dwc3_resume_irq, > - IRQF_ONESHOT | IRQF_NO_AUTOEN, > - "qcom_dwc3 SS", qcom); > - if (ret) { > - dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); > + ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq"); > + if (ret) > return ret; > - } > qcom->ss_phy_irq = irq; > } > > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > On multiport supported controllers, each port has its own DP/DM and > SuperSpeed (if super speed capable) interrupts. As per the bindings, > their interrupt names differ from single-port ones by having a "_x" > added as suffix (x being the port number). Identify from the interrupt > names whether the controller is a multiport controller or not. > Refactor dwc3_qcom_setup_irq() call to parse multiportinterrupts along > with non-multiport ones accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/dwc3-qcom.c | 140 ++++++++++++++++++++++++++--------- > 1 file changed, 106 insertions(+), 34 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index cae5dab8fcfc..5ddb694dd8e7 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -52,6 +52,16 @@ > #define APPS_USB_AVG_BW 0 > #define APPS_USB_PEAK_BW MBps_to_icc(40) > > +/* Qualcomm SoCs with multiport support has up to 4 ports */ > +#define DWC3_QCOM_MAX_PORTS 4 > + > +struct dwc3_qcom_port { > + int qusb2_phy_irq; > + int dp_hs_phy_irq; > + int dm_hs_phy_irq; > + int ss_phy_irq; > +}; > + > struct dwc3_qcom { > struct device *dev; > void __iomem *qscratch_base; > @@ -59,11 +69,8 @@ struct dwc3_qcom { > struct clk **clks; > int num_clocks; > struct reset_control *resets; > - > - int qusb2_phy_irq; > - int dp_hs_phy_irq; > - int dm_hs_phy_irq; > - int ss_phy_irq; > + struct dwc3_qcom_port ports[DWC3_QCOM_MAX_PORTS]; > + u8 num_ports; > enum usb_device_speed usb2_speed; > > struct extcon_dev *edev; > @@ -354,24 +361,24 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) > > static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) > { > - dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].qusb2_phy_irq); > > if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > } else { > - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); > - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > } > > - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].ss_phy_irq); > } > > static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > { > - dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].qusb2_phy_irq, 0); > > /* > * Configure DP/DM line interrupts based on the USB2 device attached to > @@ -383,20 +390,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > */ > > if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, > - IRQ_TYPE_EDGE_FALLING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + IRQ_TYPE_EDGE_FALLING); > } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, > - IRQ_TYPE_EDGE_FALLING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + IRQ_TYPE_EDGE_FALLING); > } else { > - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, > - IRQ_TYPE_EDGE_RISING); > - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, > - IRQ_TYPE_EDGE_RISING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + IRQ_TYPE_EDGE_RISING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + IRQ_TYPE_EDGE_RISING); > } > > - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].ss_phy_irq, 0); > } > > static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > @@ -517,42 +524,107 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, > return ret; > } > > -static int dwc3_qcom_setup_irq(struct platform_device *pdev) > +static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport) > { > struct dwc3_qcom *qcom = platform_get_drvdata(pdev); > + const char *irq_name; > int irq; > int ret; > > - irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->qusb2_phy_irq = irq; > + qcom->ports[port_index].dp_hs_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_irq"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->dp_hs_phy_irq = irq; > + qcom->ports[port_index].dm_hs_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "dm_hs_phy_irq"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->dm_hs_phy_irq = irq; > + qcom->ports[port_index].ss_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "ss_phy_irq"); > + if (is_multiport) > + return 0; > + > + irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); > + if (ret) > + return ret; > + qcom->ports[port_index].qusb2_phy_irq = irq; > + } > + > + return 0; > +} > + > +static int dwc3_qcom_find_num_ports(struct platform_device *pdev) > +{ > + char irq_name[14]; > + int port_num; > + int irq; > + > + irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1"); > + if (irq <= 0) > + return 1; > + > + for (port_num = 2; port_num <= DWC3_QCOM_MAX_PORTS; port_num++) { > + sprintf(irq_name, "dp_hs_phy_%d", port_num); > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > + if (irq <= 0) > + return port_num - 1; > + } > + > + return DWC3_QCOM_MAX_PORTS; > +} > + > +static int dwc3_qcom_setup_irq(struct platform_device *pdev) > +{ > + struct dwc3_qcom *qcom = platform_get_drvdata(pdev); > + bool is_multiport; > + int ret; > + int i; > + > + qcom->num_ports = dwc3_qcom_find_num_ports(pdev); > + is_multiport = (qcom->num_ports > 1); > + > + for (i = 0; i < qcom->num_ports; i++) { > + ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport); > if (ret) > return ret; > - qcom->ss_phy_irq = irq; > } > > return 0; > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > DWC3 Qcom wrapper currently supports only wakeup configuration > for single port controllers. Read speed of each port connected > to the controller and enable wakeup for each of them accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/dwc3-qcom.c | 71 +++++++++++++++++++++--------------- > 1 file changed, 41 insertions(+), 30 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index 5ddb694dd8e7..b6f13bb14e2c 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -60,6 +60,7 @@ struct dwc3_qcom_port { > int dp_hs_phy_irq; > int dm_hs_phy_irq; > int ss_phy_irq; > + enum usb_device_speed usb2_speed; > }; > > struct dwc3_qcom { > @@ -71,7 +72,6 @@ struct dwc3_qcom { > struct reset_control *resets; > struct dwc3_qcom_port ports[DWC3_QCOM_MAX_PORTS]; > u8 num_ports; > - enum usb_device_speed usb2_speed; > > struct extcon_dev *edev; > struct extcon_dev *host_edev; > @@ -310,7 +310,7 @@ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) > return dwc->xhci; > } > > -static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) > +static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom, int port_index) > { > struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); > struct usb_device *udev; > @@ -321,14 +321,8 @@ static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) > */ > hcd = platform_get_drvdata(dwc->xhci); > > - /* > - * It is possible to query the speed of all children of > - * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code > - * currently supports only 1 port per controller. So > - * this is sufficient. > - */ > #ifdef CONFIG_USB > - udev = usb_hub_find_child(hcd->self.root_hub, 1); > + udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1); > #else > udev = NULL; > #endif > @@ -359,26 +353,26 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) > disable_irq_nosync(irq); > } > > -static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) > +static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port) > { > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].qusb2_phy_irq); > + dwc3_qcom_disable_wakeup_irq(port->qusb2_phy_irq); > > - if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > - } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > - (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > + if (port->usb2_speed == USB_SPEED_LOW) { > + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); > + } else if ((port->usb2_speed == USB_SPEED_HIGH) || > + (port->usb2_speed == USB_SPEED_FULL)) { > + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); > } else { > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); > } > > - dwc3_qcom_disable_wakeup_irq(qcom->ports[0].ss_phy_irq); > + dwc3_qcom_disable_wakeup_irq(port->ss_phy_irq); > } > > -static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > +static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port) > { > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].qusb2_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0); > > /* > * Configure DP/DM line interrupts based on the USB2 device attached to > @@ -389,21 +383,37 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. > */ > > - if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + if (port->usb2_speed == USB_SPEED_LOW) { > + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, > IRQ_TYPE_EDGE_FALLING); > - } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > - (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + } else if ((port->usb2_speed == USB_SPEED_HIGH) || > + (port->usb2_speed == USB_SPEED_FULL)) { > + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, > IRQ_TYPE_EDGE_FALLING); > } else { > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, > IRQ_TYPE_EDGE_RISING); > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, > IRQ_TYPE_EDGE_RISING); > } > > - dwc3_qcom_enable_wakeup_irq(qcom->ports[0].ss_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(port->ss_phy_irq, 0); > +} > + > +static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) > +{ > + int i; > + > + for (i = 0; i < qcom->num_ports; i++) > + dwc3_qcom_disable_port_interrupts(&qcom->ports[i]); > +} > + > +static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > +{ > + int i; > + > + for (i = 0; i < qcom->num_ports; i++) > + dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); > } > > static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > @@ -430,7 +440,8 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > * freezable workqueue. > */ > if (dwc3_qcom_is_host(qcom) && wakeup) { > - qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom); > + for (i = 0; i < qcom->num_ports; i++) > + qcom->ports[i].usb2_speed = dwc3_qcom_read_usb2_speed(qcom, i); > dwc3_qcom_enable_interrupts(qcom); > } > > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Sat, Apr 20, 2024, Krishna Kurapati wrote: > Power event IRQ is used for wakeup either when the controller is > SuperSpeed capable but is missing an SuperSpeed PHY interrupt, or when > the GIC is not capable of detecting DP/DM High-Speed PHY interrupts. > > The Power event IRQ stat register indicates whether the High-Speed > phy entered and exited L2 successfully during suspend and resume. > Indicate the same for all ports of a multiport controller. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/usb/dwc3/dwc3-qcom.c | 23 +++++++++++++++++------ > 1 file changed, 17 insertions(+), 6 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index b6f13bb14e2c..88fb6706a18d 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -36,7 +36,6 @@ > #define PIPE3_PHYSTATUS_SW BIT(3) > #define PIPE_UTMI_CLK_DIS BIT(8) > > -#define PWR_EVNT_IRQ_STAT_REG 0x58 > #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) > #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) > > @@ -55,6 +54,13 @@ > /* Qualcomm SoCs with multiport support has up to 4 ports */ > #define DWC3_QCOM_MAX_PORTS 4 > > +static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = { > + 0x58, > + 0x1dc, > + 0x228, > + 0x238, > +}; > + > struct dwc3_qcom_port { > int qusb2_phy_irq; > int dp_hs_phy_irq; > @@ -424,9 +430,11 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > if (qcom->is_suspended) > return 0; > > - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); > - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) > - dev_err(qcom->dev, "HS-PHY not in L2\n"); > + for (i = 0; i < qcom->num_ports; i++) { > + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); > + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) > + dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); > + } > > for (i = qcom->num_clocks - 1; i >= 0; i--) > clk_disable_unprepare(qcom->clks[i]); > @@ -475,8 +483,11 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) > dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); > > /* Clear existing events from PHY related to L2 in/out */ > - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, > - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); > + for (i = 0; i < qcom->num_ports; i++) { > + dwc3_qcom_setbits(qcom->qscratch_base, > + pwr_evnt_irq_stat_reg[i], > + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); > + } > > qcom->is_suspended = false; > > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
Currently the DWC3 driver supports only single port controller which requires at most two PHYs ie HS and SS PHYs. There are SoCs that has DWC3 controller with multiple ports that can operate in host mode. Some of the port supports both SS+HS and other port supports only HS mode. This change primarily refactors the Phy logic in core driver to allow multiport support with Generic Phy's. The DWC3 controller supports up to 15 High-Speed phys and 4 SuperSpeed phys. The multiport controller in Qualcomm SA8295P is paired with two High-Speed + SuperSpeed and two High-Speed-only ports. It is assumed that the N SuperSpeed PHYs are paired with the first N High-Speed PHYs. Changes in v21: Updated core driver bindings to support up to 19 max items. Updated commit text in patches 2/5/6. Updated core driver to support 15 HS and 4 SS PHYs as indicated by Thinh in [1]. Chaned usage of sprintf to snprintf while reading phys in core driver. Added a separate macro for DWC3 QCOM driver for indicating max ports. Removed unused PWR_EVENT_IRQ_STAT_REG macro in patch (9/9). Code re-verified internally and added Bjorn.A RB tag for patches. Changes in v20: Modified return check in get_num_ports call. Code re-verified internally and added Bjorn.A RB Tag in patch (2/9) from internal review. Changes in v19: Replaced IS_ERR(ptr) with a NULL check. Modified name of function reading the port num in core file. Changes in v18: Updated variable names in patch-7 for setup_port_irq and find_num_ports calls. Changes in v17: Modified DT handling patch by checking if dp_hs_phy_1 is present or not and then going for DT parsing. Changes in v16: Removing ACPI has simplified the interrupt reading in wrapper. Also the logic to find number of ports is based on dp_hs_phy interrupt check in DT. Enabling and disabling interrupts is now done per port. Added info on power event irq in commit message. Changes in v15: Added minItems property in qcom,dwc3 bindings as suggested by Rob. Retained all RB's/ACK's got in v14. Changes in v14: Moved wrapper binding update to 5th patch in the series as it deals with only wakeup and not enumeration. The first part of the series deals with enumeration and the next part deals with wakeup. Updated commit text for wrapper driver patches. Added error checks in get_port_index and setup_irq call which were missing in v13. Added SOB and CDB tags appropriately for the patches. Rebased code on top of latest usb next. DT changes have been removed and will be sent as a separate series. Changes in v13: This series is a subset of patches in v11 as the first 3 patches in v11 have been mereged into usb-next. Moved dr_mode property from platform specific files to common sc8280xp DT. Fixed function call wrapping, added comments and replaced #defines with enum in dwc3-qcom for identifying IRQ index appropriately. Fixed nitpicks pointed out in v11 for suspend-resume handling. Added reported-by tag for phy refactoring patch as a compile error was found by kernel test bot [1]. Removed reviewed-by tag of maintainer for phy refactoring patch as a minor change of increasing phy-names array size by 2-bytes was done to fix compilation issue mentioned in [1]. Changes in v12: Pushed as a subset of acked but no-yet-merged patches of v11 with intent of making rebase of other patches easy. Active reviewers from community suggested that it would be better to push the whole series in one go as it would give good clarity and context for all the patches in the series. So pushed v13 for the same addressing comments received in v11. Changes in v11: Implemented port_count calculation by reading interrupt-names from DT. Refactored IRQ handling in dwc3-qcom. Moving of macros to xhci-ext-caps.h made as a separate patch. Names of interrupts to be displayed on /proc/interrupts set to the ones present in DT. Changes in v10: Refactored phy init/exit/power-on/off functions in dwc3 core Refactored dwc3-qcom irq registration and handling Implemented wakeup for multiport irq's Moved few macros from xhci.h to xhci-ext-caps.h Fixed nits pointed out in v9 Fixed Co-developed by and SOB tags in patches 5 and 11 Changes in v9: Added IRQ support for DP/DM/SS MP Irq's of SC8280 Refactored code to read port count by accessing xhci registers Changes in v8: Reorganised code in patch-5 Fixed nitpicks in code according to comments received on v7 Fixed indentation in DT patches Added drive strength for pinctrl nodes in SA8295 DT Changes in v7: Added power event irq's for Multiport controller. Udpated commit text for patch-9 (adding DT changes for enabling first port of multiport controller on sa8540-ride). Fixed check-patch warnings for driver code. Fixed DT binding errors for changes in snps,dwc3.yaml Reabsed code on top of usb-next Changes in v6: Updated comments in code after. Updated variables names appropriately as per review comments. Updated commit text in patch-2 and added additional info as per review comments. The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected it in this version. Changes in v5: Added DT support for first port of Teritiary USB controller on SA8540-Ride Added support for reading port info from XHCI Extended Params registers. Changes in RFC v4: Added DT support for SA8295p. Changes in RFC v3: Incase any PHY init fails, then clear/exit the PHYs that are already initialized. Changes in RFC v2: Changed dwc3_count_phys to return the number of PHY Phandles in the node. This will be used now in dwc3_extract_num_phys to increment num_usb2_phy and num_usb3_phy. Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its structure such that the first half is for HS-PHY and second half is for SS-PHY. In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is present, pass proper SS_IDX else pass -1. Tested enumeration interrupt registration on Tertiary controller of SA8295 ADP: / # lsusb Bus 001 Device 001: ID 1d6b:0002 Bus 002 Device 001: ID 1d6b:0003 Bus 001 Device 002: ID 046d:c06a / # / # dmesg | grep ports [ 0.066250] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.154668] dwc3 a400000.usb: K: hs-ports: 4 ss-ports: 2 [ 0.223137] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.1 Enhanced SuperSpeed [ 0.227795] hub 1-0:1.0: 4 ports detected [ 0.233724] hub 2-0:1.0: 2 ports detected Tested interrupt registration for all 4 ports of SA8295 ADP: / # cat /proc/interrupts |grep phy 162: 0 0 0 0 0 0 0 0 PDC 127 Edge dp_hs_phy_1 163: 0 0 0 0 0 0 0 0 PDC 129 Edge dp_hs_phy_2 164: 0 0 0 0 0 0 0 0 PDC 131 Edge dp_hs_phy_3 165: 0 0 0 0 0 0 0 0 PDC 133 Edge dp_hs_phy_4 166: 0 0 0 0 0 0 0 0 PDC 126 Edge dm_hs_phy_1 167: 0 0 0 0 0 0 0 0 PDC 16 Level ss_phy_1 168: 0 0 0 0 0 0 0 0 PDC 128 Edge dm_hs_phy_2 169: 0 0 0 0 0 0 0 0 PDC 17 Level ss_phy_2 170: 0 0 0 0 0 0 0 0 PDC 130 Edge dm_hs_phy_3 171: 0 0 0 0 0 0 0 0 PDC 132 Edge dm_hs_phy_4 173: 0 0 0 0 0 0 0 0 PDC 14 Edge dp_hs_phy_irq 174: 0 0 0 0 0 0 0 0 PDC 15 Edge dm_hs_phy_irq 175: 0 0 0 0 0 0 0 0 PDC 138 Level ss_phy_irq Tested working of ADB on SM8450 QRD. Links to previous versions: Link to v20: https://lore.kernel.org/all/20240408132925.1880571-1-quic_kriskura@quicinc.com/ Link to v19: https://lore.kernel.org/all/20240404051229.3082902-1-quic_kriskura@quicinc.com/ Link to v18: https://lore.kernel.org/all/20240326113253.3010447-1-quic_kriskura@quicinc.com/ Link to v17: https://lore.kernel.org/all/20240326102809.2940123-1-quic_kriskura@quicinc.com/ Link to v16: https://lore.kernel.org/all/20240307062052.2319851-1-quic_kriskura@quicinc.com/ Link to v15: https://lore.kernel.org/all/20240216005756.762712-1-quic_kriskura@quicinc.com/ Link to v14: https://lore.kernel.org/all/20240206051825.1038685-1-quic_kriskura@quicinc.com/ Link to v13: https://lore.kernel.org/all/20231007154806.605-1-quic_kriskura@quicinc.com/ Link to v12: https://lore.kernel.org/all/20231004165922.25642-1-quic_kriskura@quicinc.com/ Link to v11: https://lore.kernel.org/all/20230828133033.11988-1-quic_kriskura@quicinc.com/ Link to v10: https://lore.kernel.org/all/20230727223307.8096-1-quic_kriskura@quicinc.com/ Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@quicinc.com/ Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@quicinc.com/ Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@quicinc.com/ Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@quicinc.com/ Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/ Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/ Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r [1]: https://lore.kernel.org/linux-usb/20230801013031.ft3zpoatiyfegmh6@synopsys.com/ Krishna Kurapati (9): dt-bindings: usb: Add bindings for multiport properties on DWC3 controller usb: dwc3: core: Access XHCI address space temporarily to read port info usb: dwc3: core: Skip setting event buffers for host only controllers usb: dwc3: core: Refactor PHY logic to support Multiport Controller dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport usb: dwc3: qcom: Add helper function to request wakeup interrupts usb: dwc3: qcom: Refactor IRQ handling in glue driver usb: dwc3: qcom: Enable wakeup for applicable ports of multiport usb: dwc3: qcom: Add multiport suspend/resume support for wrapper .../devicetree/bindings/usb/qcom,dwc3.yaml | 34 ++ .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- drivers/usb/dwc3/core.c | 329 ++++++++++++++---- drivers/usb/dwc3/core.h | 20 +- drivers/usb/dwc3/drd.c | 15 +- drivers/usb/dwc3/dwc3-qcom.c | 255 +++++++++----- 6 files changed, 493 insertions(+), 173 deletions(-) base-commit: 684e9f5f97eb4b7831298ffad140d5c1d426ff27