| Message ID | 20231023-display-support-v2-0-33ce8864b227@baylibre.com |
|---|---|
| Headers | show |
| Series | Add display support for the MT8365-EVK board | expand |
Hello, On Tue, Apr 16, 2024 at 05:53:01PM +0200, Alexandre Mergnat wrote: > Alexandre Mergnat (16): > [...] > dt-bindings: pwm: mediatek,pwm-disp: add power-domains property > dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC > [...] > base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e > change-id: 20231023-display-support-c6418b30e419 I cannot find 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e, neither in next nor in stable nor in drm-misc nor in Linus' repository. For sure it's not based on next, because otherwise you'd have noticed that the power-domains property is already documented there. (Currently as fb7c3d8ba039df877886fd457538d8b24ca9c84b.) Best regards Uwe
On 17/04/2024 09:58, Uwe Kleine-König wrote: > Hello, > > On Tue, Apr 16, 2024 at 05:53:01PM +0200, Alexandre Mergnat wrote: >> Alexandre Mergnat (16): >> [...] >> dt-bindings: pwm: mediatek,pwm-disp: add power-domains property >> dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC >> [...] >> base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e >> change-id: 20231023-display-support-c6418b30e419 > > I cannot find 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e, neither in next > nor in stable nor in drm-misc nor in Linus' repository. > > For sure it's not based on next, because otherwise you'd have noticed > that the power-domains property is already documented there. (Currently > as fb7c3d8ba039df877886fd457538d8b24ca9c84b.) You're right, this V2 is based on v6.9-rc3 > > Best regards > Uwe >
Il 16/04/24 17:53, Alexandre Mergnat ha scritto: > - Add compatibles and platform data into the Mediatek DPI driver. > - Fix the DPI0 parent clock to be consistent. > > This SoC is compatible with the mt8183 calculate factor. > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > drivers/clk/mediatek/clk-mt8365-mm.c | 2 +- > drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c > index 01a2ef8f594e..3f62ec750733 100644 > --- a/drivers/clk/mediatek/clk-mt8365-mm.c > +++ b/drivers/clk/mediatek/clk-mt8365-mm.c > @@ -53,7 +53,7 @@ static const struct mtk_gate mm_clks[] = { > GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17), > GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18), > GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19), > - GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20), > + GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20), While I can agree with that change, this needs a Fixes tag and needs a commit on its own. > GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21), > GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22), > GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23), > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index beb7d9d08e97..a4f9376ee472 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -997,6 +997,23 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { > .csc_enable_bit = DPINTF_CSC_ENABLE, > }; > > +static const struct mtk_dpi_conf mt8365_conf = { > + .cal_factor = mt8183_calculate_factor, > + .reg_h_fre_con = 0xe0, > + .max_clock_khz = 150000, > + .output_fmts = mt8183_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .pixels_per_iter = 1, > + .is_ck_de_pol = true, > + .swap_input_support = true, > + .support_direct_pin = true, > + .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > + .csc_enable_bit = CSC_ENABLE, > +}; You don't need this, as that's a direct copy of `mt8192_conf`. > + > static int mtk_dpi_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -1092,6 +1109,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { > { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, > { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, > { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, > + { .compatible = "mediatek,mt8365-dpi", .data = &mt8365_conf }, ...and you don't need to add any mt8365 specific compatible in there as well, as you can simply add the node as compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; Cheers, Angelo > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); >
Il 16/04/24 17:53, Alexandre Mergnat ha scritto: > - Add aliases for each display components to help display drivers. > - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals > for the LED driver of mobile LCM. > - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane > output) > - Add the display mutex support. > - Add the following display component support: > - OVL0 (Overlay) > - RDMA0 (Data Path Read DMA) > - Color0 > - CCorr0 (Color Correction) > - AAL0 (Adaptive Ambient Light) > - GAMMA0 > - Dither0 > - DSI0 (Display Serial Interface) > - RDMA1 (Data Path Read DMA) > - DPI0 (Display Parallel Interface) > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++ > 1 file changed, 146 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index 24581f7410aa..a95f90da4491 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -8,6 +8,7 @@ > #include <dt-bindings/clock/mediatek,mt8365-clk.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/power/mediatek,mt8365-power.h> > > @@ -17,6 +18,19 @@ / { > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + aal0 = &aal0; > + ccorr0 = &ccorr0; > + color0 = &color0; > + dither0 = &dither0; > + dpi0 = &dpi0; > + dsi0 = &dsi0; > + gamma0 = &gamma0; > + ovl0 = &ovl0; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -607,6 +621,17 @@ spi: spi@1100a000 { > status = "disabled"; > }; > > + disp_pwm: pwm@1100e000 { > + compatible = "mediatek,mt8365-disp-pwm", > + "mediatek,mt8183-disp-pwm"; Fits in a single line > + reg = <0 0x1100e000 0 0x1000>; > + clock-names = "main", "mm"; > + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, > + <&infracfg CLK_IFR_DISP_PWM>; same > + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + #pwm-cells = <2>; > + }; > + > i2c3: i2c@1100f000 { > compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; > reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; > @@ -703,6 +728,15 @@ ethernet: ethernet@112a0000 { > status = "disabled"; > }; > > + mipi_tx0: dsi-phy@11c00000 { > + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; > + reg = <0 0x11c00000 0 0x800>; > + clock-output-names = "mipi_tx0_pll"; > + clocks = <&clk26m>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + }; > + > u3phy: t-phy@11cc0000 { > compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; > #address-cells = <1>; > @@ -732,6 +766,13 @@ mmsys: syscon@14000000 { > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8365-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8365-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -755,6 +796,111 @@ larb0: larb@14003000 { > mediatek,larb-id = <0>; > }; > > + ovl0: ovl@1400b000 { > + compatible = "mediatek,mt8365-disp-ovl", > + "mediatek,mt8192-disp-ovl"; single line > + reg = <0 0x1400b000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; > + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + }; > + > + rdma0: rdma@1400d000 { > + compatible = "mediatek,mt8365-disp-rdma", > + "mediatek,mt8183-disp-rdma"; ditto > + reg = <0 0x1400d000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; > + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; > + iommus = <&iommu M4U_PORT_DISP_RDMA0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; > + }; > + > + color0: color@1400f000 { > + compatible = "mediatek,mt8365-disp-color", > + "mediatek,mt8173-disp-color"; ...and all the others too (maybe not all, it's fine until 100 cols anyway) Cheers, Angelo
Il 16/04/24 17:53, Alexandre Mergnat ha scritto: > MIPI DSI: > - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", > to power the pannel plugged to the DSI connector. > - Setup the Display Parallel Interface. > - Add the startek kd070fhfid015 pannel support. > > HDMI: > - Add HDMI connector support. > - Add the "ite,it66121" HDMI bridge support, driven by I2C1. > - Setup the Display Parallel Interface. > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 182 ++++++++++++++++++++++++++++ > 1 file changed, 182 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > index 50cbaefa1a99..4afdcbefc481 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > @@ -26,6 +26,18 @@ chosen { > stdout-path = "serial0:921600n8"; > }; > > + connector { > + compatible = "hdmi-connector"; > + label = "hdmi"; > + type = "d"; > + > + port { > + hdmi_connector_in: endpoint { > + remote-endpoint = <&hdmi_connector_out>; > + }; > + }; > + }; > + > firmware { > optee { > compatible = "linaro,optee-tz"; > @@ -86,6 +98,56 @@ optee_reserved: optee@43200000 { > reg = <0 0x43200000 0 0x00c00000>; > }; > }; > + > + vsys_lcm_reg: regulator-vsys-lcm { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <5000000>; > + regulator-name = "vsys_lcm"; > + }; > +}; > + > +&dpi0 { > + pinctrl-0 = <&dpi_default_pins>; > + pinctrl-1 = <&dpi_idle_pins>; > + pinctrl-names = "default", "sleep"; > + status = "okay"; > + > + port { > + dpi_out: endpoint { > + remote-endpoint = <&it66121_in>; > + }; > + }; > +}; > + > +&dsi0 { > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + panel@0 { > + compatible = "startek,kd070fhfid015"; > + status = "okay"; status is always okay, unless it's disabled. > + reg = <0>; > + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; > + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; > + iovcc-supply = <&mt6357_vsim1_reg>; > + power-supply = <&vsys_lcm_reg>; > + > + port { > + panel_in: endpoint { > + remote-endpoint = <&dsi_out>; > + }; > + }; > + }; > + > + port { > + dsi_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > }; > > &cpu0 { > @@ -138,6 +200,50 @@ &i2c0 { > status = "okay"; > }; > > +&i2c1 { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-div = <2>; > + clock-frequency = <100000>; > + pinctrl-0 = <&i2c1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + it66121hdmitx: it66121hdmitx@4c { Can we please get an actually readable name for this node? Just a suggestion (you're free to rename however you want) it66121_hdmi: hdmi@4c { > + #sound-dai-cells = <0>; > + compatible = "ite,it66121"; > + interrupt-parent = <&pio>; > + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; > + pinctrl-0 = <&ite_pins>; > + pinctrl-names = "default"; > + reg = <0x4c>; > + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; > + vcn18-supply = <&mt6357_vsim2_reg>; > + vcn33-supply = <&mt6357_vibr_reg>; > + vrf12-supply = <&mt6357_vrf12_reg>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + it66121_in: endpoint { > + bus-width = <12>; > + remote-endpoint = <&dpi_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + hdmi_connector_out: endpoint { > + remote-endpoint = <&hdmi_connector_in>; > + }; > + }; > + }; > + }; > +}; > + > &mmc0 { > assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; > assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; > @@ -180,7 +286,55 @@ &mt6357_pmic { > #interrupt-cells = <2>; > }; > > +&mt6357_vsim1_reg { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > +}; > + > &pio { > + dpi_default_pins: dpi-default-pins { > + pins { > + pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>, > + <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>, > + <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>, > + <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>, > + <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>, > + <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>, > + <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>, > + <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>, > + <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>, > + <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>, > + <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>, > + <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>, > + <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>, > + <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>, > + <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>, > + <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>; > + drive-strength = <MTK_DRIVE_4mA>; drive-strength = <4> is just fine....! :-) > + }; > + }; > + > + dpi_idle_pins: dpi-idle-pins { > + pins { > + pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>, > + <MT8365_PIN_1_GPIO1__FUNC_GPIO1>, > + <MT8365_PIN_2_GPIO2__FUNC_GPIO2>, > + <MT8365_PIN_3_GPIO3__FUNC_GPIO3>, > + <MT8365_PIN_4_GPIO4__FUNC_GPIO4>, > + <MT8365_PIN_5_GPIO5__FUNC_GPIO5>, > + <MT8365_PIN_6_GPIO6__FUNC_GPIO6>, > + <MT8365_PIN_7_GPIO7__FUNC_GPIO7>, > + <MT8365_PIN_8_GPIO8__FUNC_GPIO8>, > + <MT8365_PIN_9_GPIO9__FUNC_GPIO9>, > + <MT8365_PIN_10_GPIO10__FUNC_GPIO10>, > + <MT8365_PIN_11_GPIO11__FUNC_GPIO11>, > + <MT8365_PIN_12_GPIO12__FUNC_GPIO12>, > + <MT8365_PIN_13_GPIO13__FUNC_GPIO13>, > + <MT8365_PIN_14_GPIO14__FUNC_GPIO14>, > + <MT8365_PIN_15_GPIO15__FUNC_GPIO15>; > + }; > + }; > + > ethernet_pins: ethernet-pins { > phy_reset_pins { > pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>; > @@ -222,6 +376,34 @@ pins { > }; > }; > > + i2c1_pins: i2c1-pins { > + pins { > + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, > + <MT8365_PIN_60_SCL1__FUNC_SCL1_0>; > + bias-pull-up; > + }; > + }; > + > + ite_pins: ite-pins { > + extra blank line, please remove. > + irq_ite_pins { Did you run dtbs_check?!? :-) Cheers, Angelo > + pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>; > + input-enable; > + bias-pull-up; > + }; > + > + pwr_pins { > + pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>, > + <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>; > + output-high; > + }; > + > + rst_ite_pins { > + pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>; > + output-high; > + }; > + }; > + > mmc0_default_pins: mmc0-default-pins { > clk-pins { > pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; >
On 17/04/2024 12:27, AngeloGioacchino Del Regno wrote: > >> + irq_ite_pins { > > Did you run dtbs_check?!? :-) Yes without error, here my command: dt-validate -s Documentation/devicetree/bindings arch/arm64/boot/dts/mediatek/mt8365-evk.dtb Also I've done a "make dtbs_check" just to be sure, nothing wrong on mt8365-evk.dtb. For you, what is the issue please ?
The purpose of this series is to add the display support for the mt8365-evk. This is the list of HWs / IPs support added: - Connectors (HW): - HDMI - MIPI DSI (Mobile Industry Processor Interface Display Serial Interface) - HDMI bridge (it66121) - DSI pannel (startek,kd070fhfid015) - SoC display blocks (IP): - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) The Mediatek DSI, DPI and DRM drivers are also improved. Regards, Alex Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- Changes in v2: - s/binding/compatible/ in commit messages/titles. - Improve commit messages as Conor suggest. - pwm-disp: Set power domain property for MT8365. This one is optionnal and can be used for other SoC. - Fix mediatek,dsi.yaml issue. - Remove the extra clock in the DPI node/driver and fix the dpi clock parenting to be consistent with the DPI clock assignement. - Link to v1: https://lore.kernel.org/r/20231023-display-support-v1-0-5c860ed5c33b@baylibre.com --- Alexandre Mergnat (16): dt-bindings: display: mediatek: aal: add compatible for MT8365 SoC dt-bindings: display: mediatek: ccorr: add compatible for MT8365 SoC dt-bindings: display: mediatek: color: add compatible for MT8365 SoC dt-bindings: display: mediatek: dither: add compatible for MT8365 SoC dt-bindings: display: mediatek: dsi: add compatible for MT8365 SoC dt-bindings: display: mediatek: dpi: add compatible for MT8365 dt-bindings: display: mediatek: gamma: add compatible for MT8365 SoC dt-bindings: display: mediatek: ovl: add compatible for MT8365 SoC dt-bindings: display: mediatek: rdma: add compatible for MT8365 SoC dt-bindings: pwm: mediatek,pwm-disp: add power-domains property dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC drm/mediatek: dsi: Improves the DSI lane setup robustness drm/mediatek: add mt8365 dpi support arm64: defconfig: enable display connector support arm64: dts: mediatek: add display blocks support for the MT8365 SoC arm64: dts: mediatek: add display support for mt8365-evk Fabien Parent (2): dt-bindings: display: mediatek: dpi: add power-domains property drm/mediatek: add MT8365 SoC support .../bindings/display/mediatek/mediatek,aal.yaml | 1 + .../bindings/display/mediatek/mediatek,ccorr.yaml | 3 + .../bindings/display/mediatek/mediatek,color.yaml | 1 + .../bindings/display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,dpi.yaml | 6 + .../bindings/display/mediatek/mediatek,dsi.yaml | 1 + .../bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 7 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 182 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/mediatek/clk-mt8365-mm.c | 2 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 2 + 17 files changed, 403 insertions(+), 1 deletion(-) --- base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e change-id: 20231023-display-support-c6418b30e419 Best regards,