| Message ID | 20240415-dev-charlie-support_thead_vector_6_9-v2-3-c7d68c603268@rivosinc.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | riscv: Support vendor extensions and xtheadvector | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Apr 15, 2024 at 09:12:00PM -0700, Charlie Jenkins wrote: > vendorid are required during DT parsing to determine known hardware > capabilities. This parsing happens before the whole system has booted, > so only the boot hart is online and able to report the value of its > vendorid. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> If we are gonna add these, I think we may as well add all 3. I'd also tie them together, so that either you have none or all 3. Cheers, Conor. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d87dd50f1a4b..030c7697d3b7 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -94,6 +94,11 @@ properties: > description: > The blocksize in bytes for the Zicboz cache operations. > > + riscv,vendorid: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Same value as the mvendorid CSR. > + > # RISC-V has multiple properties for cache op block sizes as the sizes > # differ between individual CBO extensions > cache-op-block-size: false > > -- > 2.44.0 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..030c7697d3b7 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -94,6 +94,11 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. + riscv,vendorid: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Same value as the mvendorid CSR. + # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false
vendorid are required during DT parsing to determine known hardware capabilities. This parsing happens before the whole system has booted, so only the boot hart is online and able to report the value of its vendorid. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+)