| Message ID | 20240403213902.26391-1-james.quinlan@broadcom.com |
|---|---|
| Headers | show |
| Series | PCI: brcmstb: Configure appropriate HW CLKREQ# mode | expand |
Hi Jim, Jim Quinlan <james.quinlan@broadcom.com> (2024-04-03): > v9 -- v8 was setting an internal bus timeout to accomodate large L1 exit > latencies. After meeting the PCIe HW team it was revealed that the > HW default timeout value was set low for the purposes of HW debugging > convenience; for nominal operation it needs to be set to a higher > value independent of this submission's purpose. This is now a > separate commit. > > -- With v8, Bjorne asked what was preventing a device from exceeding the > time required for the above internal bus timeout. The answer to this > is for us to set the endpoints' max latency {no-,}snoop value to > something below this internal timeout value. If the endpoint > respects this value as it should, it will not send an LTR request > with a larger latency value and not put itself in a situation > that requires more latency than is possible for the platform. > > Typically, ACPI or FW sets these max latency values. In most of our > systems we do not have this happening so it is up to the RC driver to > set these values in the endpoint devices. If the endpoints already > have non-zero values that are lower than what we are setting, we let > them be, as it is possible ACPI or FW set them and knows something > that we do not. > > -- The "clkreq" commit has only been changed to remove the code that was > setting the timeout value, as this code is now its own commit. Given the bot's feedback, I took the liberty of running tests on your patch series except with an extra “static” keyword. On my build system, gcc 12 wasn't complaining about it but I didn't spend time trying to find the right options, or trying a switch to clang to confirm the before/after situation: -void brcm_set_downstream_devs_ltr_max(struct brcm_pcie *pcie) +static void brcm_set_downstream_devs_ltr_max(struct brcm_pcie *pcie) Anyway, this is still: Tested-by: Cyril Brulebois <cyril@debamax.com> Test setup: ----------- - using a $CM with the 20230111 EEPROM - on the same CM4 IO Board - with a $PCIE board (PCIe to multiple USB ports) - and the same Samsung USB flash drive + Logitech keyboard. where $CM is one of: - CM4 Lite Rev 1.0 - CM4 8/32 Rev 1.0 - CM4 4/32 Rev 1.1 and $PCIE is one of: - SupaHub PCE6U1C-R02, VER 006 - SupaHub PCE6U1C-R02, VER 006S - Waveshare VIA VL805/806-based Results: -------- 1. Given this is already v9, and given I don't see how this could have possibly changed, I didn't build or tested an unpatched kernel, which I would still expect to produce either a successful boot *without* seeing the devices plugged on the PCIe-to-USB board or the dreaded SError in most cases. 2. With a patched kernel (v6.7-562-g9f8413c4a66f2 + this series + “static” in front of brcm_set_downstream_devs_ltr_max()), for all $CM/$PCIE combinations, I'm getting a system that boots, sees the flash drive, and gives decent read/write performance on it (plus a functional keyboard). Cheers,
On Wed, Apr 3, 2024 at 5:39 PM Jim Quinlan <james.quinlan@broadcom.com> wrote: > > v9 -- v8 was setting an internal bus timeout to accomodate large L1 exit > latencies. After meeting the PCIe HW team it was revealed that the > HW default timeout value was set low for the purposes of HW debugging > convenience; for nominal operation it needs to be set to a higher > value independent of this submission's purpose. This is now a > separate commit. Bjorn, Did you have some time to look at this? Do you have any comments or questions? Regards, Jim Quinlan Broadcom STB/CM > > -- With v8, Bjorne asked what was preventing a device from exceeding the > time required for the above internal bus timeout. The answer to this > is for us to set the endpoints' max latency {no-,}snoop value to > something below this internal timeout value. If the endpoint > respects this value as it should, it will not send an LTR request > with a larger latency value and not put itself in a situation > that requires more latency than is possible for the platform. > > Typically, ACPI or FW sets these max latency values. In most of our > systems we do not have this happening so it is up to the RC driver to > set these values in the endpoint devices. If the endpoints already > have non-zero values that are lower than what we are setting, we let > them be, as it is possible ACPI or FW set them and knows something > that we do not. > > -- The "clkreq" commit has only been changed to remove the code that was > setting the timeout value, as this code is now its own commit. > > v8 -- Un-advertise L1SS capability when in "no-l1ss" mode (Bjorn) > -- Squashed last two commits of v7 (Bjorn) > -- Fix DT binding description text wrapping (Bjorn) > -- Fix incorrect Spec reference (Bjorn) > s/PCIe Spec/PCIe Express Mini CEM 2.1 specification/ > -- Text substitutions (Bjorn) > s/WRT/With respect to/ > s/Tclron/T_CLRon/ > > v7 -- Manivannan Sadhasivam suggested (a) making the property look like a > network phy-mode and (b) keeping the code simple (not counting clkreq > signal appearances, un-advertising capabilites, etc). This is > what I have done. The property is now "brcm,clkreq-mode" and > the values may be one of "safe", "default", and "no-l1ss". The > default setting is to employ the most capable power savings mode. > > v6 -- No code has been changed. > -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril) > -- Changed sign-off and author email address for all commits. > This was due to a change in Broadcom's upstreaming policy. > > v5 -- Remove DT property "brcm,completion-timeout-us" from > "DT bindings" commit. Although this error may be reported > as a completion timeout, its cause was traced to an > internal bus timeout which may occur even when there is > no PCIe access being processed. We set a timeout of four > seconds only if we are operating in "L1SS CLKREQ#" mode. > -- Correct CEM 2.0 reference provided by HW engineer, > s/3.2.5.2.5/3.2.5.2.2/ (Bjorn) > -- Add newline to dev_info() string (Stefan) > -- Change variable rval to unsigned (Stefan) > -- s/implementaion/implementation/ (Bjorn) > -- s/superpowersave/powersupersave/ (Bjorn) > -- Slightly modify message on "PERST#" commit. > -- Rebase to torvalds master > > v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC > driver probe() time. This is done in Raspian Linux and its > absence may be the cause of a failing test case. > -- New commit that removes stale comment. > > v3 -- Rewrote commit msgs and comments refering panics if L1SS > is enabled/disabled; the code snippet that unadvertises L1SS > eliminates the panic scenario. (Bjorn) > -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn) > -- Put binding names in DT commit Subject (Bjorn) > -- Add a verb to a commit's subject line (Bjorn) > -- s/accomodat(\w+)/accommodat$1/g (Bjorn) > -- Rewrote commit msgs and comments refering panics if L1SS > is enabled/disabled; the code snippet that unadvertises L1SS > eliminates the panic scenario. (Bjorn) > > v2 -- Changed binding property 'brcm,completion-timeout-msec' to > 'brcm,completion-timeout-us'. (StefanW for standard suffix). > -- Warn when clamping timeout value, and include clamped > region in message. Also add min and max in YAML. (StefanW) > -- Qualify description of "brcm,completion-timeout-us" so that > it refers to PCIe transactions. (StefanW) > -- Remvove mention of Linux specifics in binding description. (StefanW) > -- s/clkreq#/CLKREQ#/g (Bjorn) > -- Refactor completion-timeout-us code to compare max and min to > value given by the property (as opposed to the computed value). > > v1 -- The current driver assumes the downstream devices can > provide CLKREQ# for ASPM. These commits accomodate devices > w/ or w/o clkreq# and also handle L1SS-capable devices. > > -- The Raspian Linux folks have already been using a PCIe RC > property "brcm,enable-l1ss". These commits use the same > property, in a backward-compatible manner, and the implementaion > adds more detail and also automatically identifies devices w/o > a clkreq# signal, i.e. most devices plugged into an RPi CM4 > IO board. > > Jim Quinlan (4): > dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" > PCI: brcmstb: Set reasonable value for internal bus timeout > PCI: brcmstb: Set downstream maximum {no-}snoop LTR values > PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream > device > > .../bindings/pci/brcm,stb-pcie.yaml | 18 ++ > drivers/pci/controller/pcie-brcmstb.c | 161 +++++++++++++++++- > 2 files changed, 170 insertions(+), 9 deletions(-) > > > base-commit: 9f8413c4a66f2fb776d3dc3c9ed20bf435eb305e > -- > 2.17.1 >
On Tue, Apr 30, 2024 at 05:02:45PM -0400, Jim Quinlan wrote: > On Wed, Apr 3, 2024 at 5:39 PM Jim Quinlan <james.quinlan@broadcom.com> wrote: > > > > v9 -- v8 was setting an internal bus timeout to accomodate large L1 exit > > latencies. After meeting the PCIe HW team it was revealed that the > > HW default timeout value was set low for the purposes of HW debugging > > convenience; for nominal operation it needs to be set to a higher > > value independent of this submission's purpose. This is now a > > separate commit. > > Bjorn, > > Did you have some time to look at this? Do you have any comments or questions? Sorry, I didn't realize you were waiting on me. I think Krzysztof W. will ultimately take care of these. I have some minor comments but overall I'm fine with this. > > -- With v8, Bjorne asked what was preventing a device from exceeding the > > time required for the above internal bus timeout. The answer to this > > is for us to set the endpoints' max latency {no-,}snoop value to > > something below this internal timeout value. If the endpoint > > respects this value as it should, it will not send an LTR request > > with a larger latency value and not put itself in a situation > > that requires more latency than is possible for the platform. > > > > Typically, ACPI or FW sets these max latency values. In most of our > > systems we do not have this happening so it is up to the RC driver to > > set these values in the endpoint devices. If the endpoints already > > have non-zero values that are lower than what we are setting, we let > > them be, as it is possible ACPI or FW set them and knows something > > that we do not. > > > > -- The "clkreq" commit has only been changed to remove the code that was > > setting the timeout value, as this code is now its own commit. > > > > v8 -- Un-advertise L1SS capability when in "no-l1ss" mode (Bjorn) > > -- Squashed last two commits of v7 (Bjorn) > > -- Fix DT binding description text wrapping (Bjorn) > > -- Fix incorrect Spec reference (Bjorn) > > s/PCIe Spec/PCIe Express Mini CEM 2.1 specification/ > > -- Text substitutions (Bjorn) > > s/WRT/With respect to/ > > s/Tclron/T_CLRon/ > > > > v7 -- Manivannan Sadhasivam suggested (a) making the property look like a > > network phy-mode and (b) keeping the code simple (not counting clkreq > > signal appearances, un-advertising capabilites, etc). This is > > what I have done. The property is now "brcm,clkreq-mode" and > > the values may be one of "safe", "default", and "no-l1ss". The > > default setting is to employ the most capable power savings mode. > > > > v6 -- No code has been changed. > > -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril) > > -- Changed sign-off and author email address for all commits. > > This was due to a change in Broadcom's upstreaming policy. > > > > v5 -- Remove DT property "brcm,completion-timeout-us" from > > "DT bindings" commit. Although this error may be reported > > as a completion timeout, its cause was traced to an > > internal bus timeout which may occur even when there is > > no PCIe access being processed. We set a timeout of four > > seconds only if we are operating in "L1SS CLKREQ#" mode. > > -- Correct CEM 2.0 reference provided by HW engineer, > > s/3.2.5.2.5/3.2.5.2.2/ (Bjorn) > > -- Add newline to dev_info() string (Stefan) > > -- Change variable rval to unsigned (Stefan) > > -- s/implementaion/implementation/ (Bjorn) > > -- s/superpowersave/powersupersave/ (Bjorn) > > -- Slightly modify message on "PERST#" commit. > > -- Rebase to torvalds master > > > > v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC > > driver probe() time. This is done in Raspian Linux and its > > absence may be the cause of a failing test case. > > -- New commit that removes stale comment. > > > > v3 -- Rewrote commit msgs and comments refering panics if L1SS > > is enabled/disabled; the code snippet that unadvertises L1SS > > eliminates the panic scenario. (Bjorn) > > -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn) > > -- Put binding names in DT commit Subject (Bjorn) > > -- Add a verb to a commit's subject line (Bjorn) > > -- s/accomodat(\w+)/accommodat$1/g (Bjorn) > > -- Rewrote commit msgs and comments refering panics if L1SS > > is enabled/disabled; the code snippet that unadvertises L1SS > > eliminates the panic scenario. (Bjorn) > > > > v2 -- Changed binding property 'brcm,completion-timeout-msec' to > > 'brcm,completion-timeout-us'. (StefanW for standard suffix). > > -- Warn when clamping timeout value, and include clamped > > region in message. Also add min and max in YAML. (StefanW) > > -- Qualify description of "brcm,completion-timeout-us" so that > > it refers to PCIe transactions. (StefanW) > > -- Remvove mention of Linux specifics in binding description. (StefanW) > > -- s/clkreq#/CLKREQ#/g (Bjorn) > > -- Refactor completion-timeout-us code to compare max and min to > > value given by the property (as opposed to the computed value). > > > > v1 -- The current driver assumes the downstream devices can > > provide CLKREQ# for ASPM. These commits accomodate devices > > w/ or w/o clkreq# and also handle L1SS-capable devices. > > > > -- The Raspian Linux folks have already been using a PCIe RC > > property "brcm,enable-l1ss". These commits use the same > > property, in a backward-compatible manner, and the implementaion > > adds more detail and also automatically identifies devices w/o > > a clkreq# signal, i.e. most devices plugged into an RPi CM4 > > IO board. > > > > Jim Quinlan (4): > > dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" > > PCI: brcmstb: Set reasonable value for internal bus timeout > > PCI: brcmstb: Set downstream maximum {no-}snoop LTR values > > PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream > > device > > > > .../bindings/pci/brcm,stb-pcie.yaml | 18 ++ > > drivers/pci/controller/pcie-brcmstb.c | 161 +++++++++++++++++- > > 2 files changed, 170 insertions(+), 9 deletions(-) > > > > > > base-commit: 9f8413c4a66f2fb776d3dc3c9ed20bf435eb305e > > -- > > 2.17.1 > >
v9 -- v8 was setting an internal bus timeout to accomodate large L1 exit latencies. After meeting the PCIe HW team it was revealed that the HW default timeout value was set low for the purposes of HW debugging convenience; for nominal operation it needs to be set to a higher value independent of this submission's purpose. This is now a separate commit. -- With v8, Bjorne asked what was preventing a device from exceeding the time required for the above internal bus timeout. The answer to this is for us to set the endpoints' max latency {no-,}snoop value to something below this internal timeout value. If the endpoint respects this value as it should, it will not send an LTR request with a larger latency value and not put itself in a situation that requires more latency than is possible for the platform. Typically, ACPI or FW sets these max latency values. In most of our systems we do not have this happening so it is up to the RC driver to set these values in the endpoint devices. If the endpoints already have non-zero values that are lower than what we are setting, we let them be, as it is possible ACPI or FW set them and knows something that we do not. -- The "clkreq" commit has only been changed to remove the code that was setting the timeout value, as this code is now its own commit. v8 -- Un-advertise L1SS capability when in "no-l1ss" mode (Bjorn) -- Squashed last two commits of v7 (Bjorn) -- Fix DT binding description text wrapping (Bjorn) -- Fix incorrect Spec reference (Bjorn) s/PCIe Spec/PCIe Express Mini CEM 2.1 specification/ -- Text substitutions (Bjorn) s/WRT/With respect to/ s/Tclron/T_CLRon/ v7 -- Manivannan Sadhasivam suggested (a) making the property look like a network phy-mode and (b) keeping the code simple (not counting clkreq signal appearances, un-advertising capabilites, etc). This is what I have done. The property is now "brcm,clkreq-mode" and the values may be one of "safe", "default", and "no-l1ss". The default setting is to employ the most capable power savings mode. v6 -- No code has been changed. -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril) -- Changed sign-off and author email address for all commits. This was due to a change in Broadcom's upstreaming policy. v5 -- Remove DT property "brcm,completion-timeout-us" from "DT bindings" commit. Although this error may be reported as a completion timeout, its cause was traced to an internal bus timeout which may occur even when there is no PCIe access being processed. We set a timeout of four seconds only if we are operating in "L1SS CLKREQ#" mode. -- Correct CEM 2.0 reference provided by HW engineer, s/3.2.5.2.5/3.2.5.2.2/ (Bjorn) -- Add newline to dev_info() string (Stefan) -- Change variable rval to unsigned (Stefan) -- s/implementaion/implementation/ (Bjorn) -- s/superpowersave/powersupersave/ (Bjorn) -- Slightly modify message on "PERST#" commit. -- Rebase to torvalds master v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC driver probe() time. This is done in Raspian Linux and its absence may be the cause of a failing test case. -- New commit that removes stale comment. v3 -- Rewrote commit msgs and comments refering panics if L1SS is enabled/disabled; the code snippet that unadvertises L1SS eliminates the panic scenario. (Bjorn) -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn) -- Put binding names in DT commit Subject (Bjorn) -- Add a verb to a commit's subject line (Bjorn) -- s/accomodat(\w+)/accommodat$1/g (Bjorn) -- Rewrote commit msgs and comments refering panics if L1SS is enabled/disabled; the code snippet that unadvertises L1SS eliminates the panic scenario. (Bjorn) v2 -- Changed binding property 'brcm,completion-timeout-msec' to 'brcm,completion-timeout-us'. (StefanW for standard suffix). -- Warn when clamping timeout value, and include clamped region in message. Also add min and max in YAML. (StefanW) -- Qualify description of "brcm,completion-timeout-us" so that it refers to PCIe transactions. (StefanW) -- Remvove mention of Linux specifics in binding description. (StefanW) -- s/clkreq#/CLKREQ#/g (Bjorn) -- Refactor completion-timeout-us code to compare max and min to value given by the property (as opposed to the computed value). v1 -- The current driver assumes the downstream devices can provide CLKREQ# for ASPM. These commits accomodate devices w/ or w/o clkreq# and also handle L1SS-capable devices. -- The Raspian Linux folks have already been using a PCIe RC property "brcm,enable-l1ss". These commits use the same property, in a backward-compatible manner, and the implementaion adds more detail and also automatically identifies devices w/o a clkreq# signal, i.e. most devices plugged into an RPi CM4 IO board. Jim Quinlan (4): dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" PCI: brcmstb: Set reasonable value for internal bus timeout PCI: brcmstb: Set downstream maximum {no-}snoop LTR values PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device .../bindings/pci/brcm,stb-pcie.yaml | 18 ++ drivers/pci/controller/pcie-brcmstb.c | 161 +++++++++++++++++- 2 files changed, 170 insertions(+), 9 deletions(-) base-commit: 9f8413c4a66f2fb776d3dc3c9ed20bf435eb305e