Message ID | 20240326113253.3010447-1-quic_kriskura@quicinc.com |
---|---|
Headers | show |
Series | Add multiport support for DWC3 controllers | expand |
On Tue, Mar 26, 2024 at 05:02:44PM +0530, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller which > requires at most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS > mode. > > This change primarily refactors the Phy logic in core driver to allow > multiport support with Generic Phy's. > > Changes have been tested on QCOM SoC SA8295P which has 4 ports (2 > are HS+SS capable and 2 are HS only capable). > > This series depends on removal of ACPI from DWC3 QCOM wrapper [1]. > [1]: https://lore.kernel.org/all/20240305093216.3814787-1-quic_kriskura@quicinc.com/ Just to be clear, this dependency is already in 6.9-rc1 and this series is ready to be merged. > Krishna Kurapati (9): > dt-bindings: usb: Add bindings for multiport properties on DWC3 > controller > usb: dwc3: core: Access XHCI address space temporarily to read port > info > usb: dwc3: core: Skip setting event buffers for host only controllers > usb: dwc3: core: Refactor PHY logic to support Multiport Controller > dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport > usb: dwc3: qcom: Add helper function to request wakeup interrupts > usb: dwc3: qcom: Refactor IRQ handling in glue driver > usb: dwc3: qcom: Enable wakeup for applicable ports of multiport > usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Johan
On Tue, Mar 26, 2024, Krishna Kurapati wrote: > All DWC3 Multi Port controllers that exist today only support host mode. > Temporarily map XHCI address space for host-only controllers and parse > XHCI Extended Capabilities registers to read number of usb2 ports and > usb3 ports present on multiport controller. Each USB Port is at least HS > capable. > > The port info for usb2 and usb3 phy are identified as num_usb2_ports > and num_usb3_ports. The intention is as follows: > > Wherever we need to perform phy operations like: > > LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS() > { > phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); > phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); > } > > If number of usb2 ports is 3, loop can go from index 0-2 for > usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure, > if the first 2 ports are SS capable or some other ports like (2 and 3) > are SS capable. So instead, num_usb2_ports is used to loop around all > phy's (both hs and ss) for performing phy operations. If any > usb3_generic_phy turns out to be NULL, phy operation just bails out. > num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up > phy's as we need to know how many SS capable ports are there for this. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > --- > drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++ > drivers/usb/dwc3/core.h | 5 ++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 3e55838c0001..fab7664c12c0 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -39,6 +39,7 @@ > #include "io.h" > > #include "debug.h" > +#include "../host/xhci-ext-caps.h" > > #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ > > @@ -1879,10 +1880,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc) > return 0; > } > > +static int dwc3_read_port_info(struct dwc3 *dwc) > +{ > + void __iomem *base; > + u8 major_revision; > + u32 offset; > + u32 val; > + > + /* > + * Remap xHCI address space to access XHCI ext cap regs since it is > + * needed to get information on number of ports present. > + */ > + base = ioremap(dwc->xhci_resources[0].start, > + resource_size(&dwc->xhci_resources[0])); > + if (IS_ERR(base)) > + return PTR_ERR(base); Looks like you forgot to address some of the comments you said you'd update previously if you submit a new version to the series. [*] https://lore.kernel.org/linux-usb/af73110d-e13e-4183-af11-aed869ac0a31@quicinc.com/ BR, Thinh > + > + offset = 0; > + do { > + offset = xhci_find_next_ext_cap(base, offset, > + XHCI_EXT_CAPS_PROTOCOL); > + if (!offset) > + break; > + > + val = readl(base + offset); > + major_revision = XHCI_EXT_PORT_MAJOR(val); > + > + val = readl(base + offset + 0x08); > + if (major_revision == 0x03) { > + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); > + } else if (major_revision <= 0x02) { > + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); > + } else { > + dev_warn(dwc->dev, "unrecognized port major revision %d\n", > + major_revision); > + } > + } while (1); > + > + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", > + dwc->num_usb2_ports, dwc->num_usb3_ports); > + > + iounmap(base); > + > + return 0; > +} > + > static int dwc3_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct resource *res, dwc_res; > + unsigned int hw_mode; > void __iomem *regs; > struct dwc3 *dwc; > int ret; > @@ -1966,6 +2013,20 @@ static int dwc3_probe(struct platform_device *pdev) > goto err_disable_clks; > } > > + /* > + * Currently only DWC3 controllers that are host-only capable > + * can have more than one port. > + */ > + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); > + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { > + ret = dwc3_read_port_info(dwc); > + if (ret) > + goto err_disable_clks; > + } else { > + dwc->num_usb2_ports = 1; > + dwc->num_usb3_ports = 1; > + } > + > spin_lock_init(&dwc->lock); > mutex_init(&dwc->mutex); > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index c07edfc954f7..40b00a895a2a 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -1039,6 +1039,8 @@ struct dwc3_scratchpad_array { > * @usb3_phy: pointer to USB3 PHY > * @usb2_generic_phy: pointer to USB2 PHY > * @usb3_generic_phy: pointer to USB3 PHY > + * @num_usb2_ports: number of USB2 ports > + * @num_usb3_ports: number of USB3 ports > * @phys_ready: flag to indicate that PHYs are ready > * @ulpi: pointer to ulpi interface > * @ulpi_ready: flag to indicate that ULPI is initialized > @@ -1186,6 +1188,9 @@ struct dwc3 { > struct phy *usb2_generic_phy; > struct phy *usb3_generic_phy; > > + u8 num_usb2_ports; > + u8 num_usb3_ports; > + > bool phys_ready; > > struct ulpi *ulpi; > -- > 2.34.1 >
On 4/3/2024 5:02 AM, Thinh Nguyen wrote: > On Tue, Mar 26, 2024, Krishna Kurapati wrote: >> All DWC3 Multi Port controllers that exist today only support host mode. >> Temporarily map XHCI address space for host-only controllers and parse >> XHCI Extended Capabilities registers to read number of usb2 ports and >> usb3 ports present on multiport controller. Each USB Port is at least HS >> capable. >> >> The port info for usb2 and usb3 phy are identified as num_usb2_ports >> and num_usb3_ports. The intention is as follows: >> >> Wherever we need to perform phy operations like: >> >> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS() >> { >> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); >> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); >> } >> >> If number of usb2 ports is 3, loop can go from index 0-2 for >> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure, >> if the first 2 ports are SS capable or some other ports like (2 and 3) >> are SS capable. So instead, num_usb2_ports is used to loop around all >> phy's (both hs and ss) for performing phy operations. If any >> usb3_generic_phy turns out to be NULL, phy operation just bails out. >> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up >> phy's as we need to know how many SS capable ports are there for this. >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> >> --- >> drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++ >> drivers/usb/dwc3/core.h | 5 ++++ >> 2 files changed, 66 insertions(+) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >> index 3e55838c0001..fab7664c12c0 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -39,6 +39,7 @@ >> #include "io.h" >> >> #include "debug.h" >> +#include "../host/xhci-ext-caps.h" >> >> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ >> >> @@ -1879,10 +1880,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc) >> return 0; >> } >> >> +static int dwc3_read_port_info(struct dwc3 *dwc) >> +{ >> + void __iomem *base; >> + u8 major_revision; >> + u32 offset; >> + u32 val; >> + >> + /* >> + * Remap xHCI address space to access XHCI ext cap regs since it is >> + * needed to get information on number of ports present. >> + */ >> + base = ioremap(dwc->xhci_resources[0].start, >> + resource_size(&dwc->xhci_resources[0])); >> + if (IS_ERR(base)) >> + return PTR_ERR(base); > > Looks like you forgot to address some of the comments you said you'd > update previously if you submit a new version to the series. > > [*] https://lore.kernel.org/linux-usb/af73110d-e13e-4183-af11-aed869ac0a31@quicinc.com/ > Apologies. I agree. I was too much focused on acpi removal and interrupt cleanup, I forgot the last comment you gave. Can I send in a separate patch for this ? Regards, Krishna,
On Wed, Apr 03, 2024 at 10:54:25AM +0530, Krishna Kurapati PSSNV wrote: > >> +static int dwc3_read_port_info(struct dwc3 *dwc) > >> +{ > >> + void __iomem *base; > >> + u8 major_revision; > >> + u32 offset; > >> + u32 val; > >> + > >> + /* > >> + * Remap xHCI address space to access XHCI ext cap regs since it is > >> + * needed to get information on number of ports present. > >> + */ > >> + base = ioremap(dwc->xhci_resources[0].start, > >> + resource_size(&dwc->xhci_resources[0])); > >> + if (IS_ERR(base)) > >> + return PTR_ERR(base); > > > > Looks like you forgot to address some of the comments you said you'd > > update previously if you submit a new version to the series. > > > > [*] https://lore.kernel.org/linux-usb/af73110d-e13e-4183-af11-aed869ac0a31@quicinc.com/ > > > > Apologies. I agree. I was too much focused on acpi removal and interrupt > cleanup, I forgot the last comment you gave. > > Can I send in a separate patch for this ? The series has not been merged yet so you can address both issues in a v19. Perhaps wait a day or two in case Thinh has further comments. Johan
On 4/3/2024 12:36 PM, Johan Hovold wrote: > On Wed, Apr 03, 2024 at 10:54:25AM +0530, Krishna Kurapati PSSNV wrote: > >>>> +static int dwc3_read_port_info(struct dwc3 *dwc) >>>> +{ >>>> + void __iomem *base; >>>> + u8 major_revision; >>>> + u32 offset; >>>> + u32 val; >>>> + >>>> + /* >>>> + * Remap xHCI address space to access XHCI ext cap regs since it is >>>> + * needed to get information on number of ports present. >>>> + */ >>>> + base = ioremap(dwc->xhci_resources[0].start, >>>> + resource_size(&dwc->xhci_resources[0])); >>>> + if (IS_ERR(base)) >>>> + return PTR_ERR(base); >>> >>> Looks like you forgot to address some of the comments you said you'd >>> update previously if you submit a new version to the series. >>> >>> [*] https://lore.kernel.org/linux-usb/af73110d-e13e-4183-af11-aed869ac0a31@quicinc.com/ >>> >> >> Apologies. I agree. I was too much focused on acpi removal and interrupt >> cleanup, I forgot the last comment you gave. >> >> Can I send in a separate patch for this ? > > The series has not been merged yet so you can address both issues in a > v19. Perhaps wait a day or two in case Thinh has further comments. > Sure Johan. Also after making the following two changes: 1. Rename dwc3_read_port_info(...) to dwc3_get_num_ports(...) 2. Changing "if (IS_ERR(base))" to "if (!base)" Can I still retain your RB tag ? Regards, Krishna,
On Wed, Apr 03, 2024 at 01:03:21PM +0530, Krishna Kurapati PSSNV wrote: > On 4/3/2024 12:36 PM, Johan Hovold wrote: > > The series has not been merged yet so you can address both issues in a > > v19. Perhaps wait a day or two in case Thinh has further comments. > Also after making the following two changes: > > 1. Rename dwc3_read_port_info(...) to dwc3_get_num_ports(...) > 2. Changing "if (IS_ERR(base))" to "if (!base)" > > Can I still retain your RB tag ? Yes, please do. Johan