| Message ID | 20240326222844.1422948-9-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PFC support for Renesas RZ/V2H(P) SoC | expand |
Hi, Prabhakar, On 27.03.2024 00:28, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. > However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls > writing to both PFC and PMC registers. To accommodate these differences > across SoC variants, introduce set_pfc_mode() and pm_set_pfc() function > pointers. I think the overall code can be simplified if you add 1 function that does the lock/unlock for PWPR. See patch 13. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 705372faaeff..4cdebdbd8a04 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -246,6 +246,8 @@ struct rzg2l_variable_pin_cfg { > u32 pin:3; > }; > > +struct rzg2l_pinctrl; > + > struct rzg2l_pinctrl_data { > const char * const *port_pins; > const u64 *port_pin_configs; > @@ -256,6 +258,8 @@ struct rzg2l_pinctrl_data { > const struct rzg2l_hwcfg *hwcfg; > const struct rzg2l_variable_pin_cfg *variable_pin_cfg; > unsigned int n_variable_pin_cfg; > + void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); > + void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); > }; > > /** > @@ -526,7 +530,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, > dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", > RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); > > - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); > + pctrl->data->set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); > } > > return 0; > @@ -2607,7 +2611,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) > writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); > } > > - rzg2l_pinctrl_pm_setup_pfc(pctrl); > + pctrl->data->pm_set_pfc(pctrl); > rzg2l_pinctrl_pm_setup_regs(pctrl, false); > rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); > rzg2l_gpio_irq_restore(pctrl); > @@ -2672,6 +2676,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { > .variable_pin_cfg = r9a07g043f_variable_pin_cfg, > .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), > #endif > + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, > + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, > }; > > static struct rzg2l_pinctrl_data r9a07g044_data = { > @@ -2683,6 +2689,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { > .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + > ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), > .hwcfg = &rzg2l_hwcfg, > + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, > + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, > }; > > static struct rzg2l_pinctrl_data r9a08g045_data = { > @@ -2693,6 +2701,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { > .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, > .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), > .hwcfg = &rzg3s_hwcfg, > + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, > + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, > }; > > static const struct of_device_id rzg2l_pinctrl_of_table[] = {
On 28.03.2024 10:02, claudiu beznea wrote: > Hi, Prabhakar, > > On 27.03.2024 00:28, Prabhakar wrote: >> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >> >> On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. >> However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls >> writing to both PFC and PMC registers. To accommodate these differences >> across SoC variants, introduce set_pfc_mode() and pm_set_pfc() function >> pointers. > > I think the overall code can be simplified if you add 1 function that does > the lock/unlock for PWPR. See patch 13. I meant to say one function for lock and one for unlock. > >> >> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >> --- >> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 ++++++++++++-- >> 1 file changed, 12 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c >> index 705372faaeff..4cdebdbd8a04 100644 >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c >> @@ -246,6 +246,8 @@ struct rzg2l_variable_pin_cfg { >> u32 pin:3; >> }; >> >> +struct rzg2l_pinctrl; >> + >> struct rzg2l_pinctrl_data { >> const char * const *port_pins; >> const u64 *port_pin_configs; >> @@ -256,6 +258,8 @@ struct rzg2l_pinctrl_data { >> const struct rzg2l_hwcfg *hwcfg; >> const struct rzg2l_variable_pin_cfg *variable_pin_cfg; >> unsigned int n_variable_pin_cfg; >> + void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); >> + void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); >> }; >> >> /** >> @@ -526,7 +530,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, >> dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", >> RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); >> >> - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); >> + pctrl->data->set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); >> } >> >> return 0; >> @@ -2607,7 +2611,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) >> writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); >> } >> >> - rzg2l_pinctrl_pm_setup_pfc(pctrl); >> + pctrl->data->pm_set_pfc(pctrl); >> rzg2l_pinctrl_pm_setup_regs(pctrl, false); >> rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); >> rzg2l_gpio_irq_restore(pctrl); >> @@ -2672,6 +2676,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { >> .variable_pin_cfg = r9a07g043f_variable_pin_cfg, >> .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), >> #endif >> + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, >> + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, >> }; >> >> static struct rzg2l_pinctrl_data r9a07g044_data = { >> @@ -2683,6 +2689,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { >> .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + >> ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), >> .hwcfg = &rzg2l_hwcfg, >> + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, >> + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, >> }; >> >> static struct rzg2l_pinctrl_data r9a08g045_data = { >> @@ -2693,6 +2701,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { >> .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, >> .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), >> .hwcfg = &rzg3s_hwcfg, >> + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, >> + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, >> }; >> >> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
Hi Claudiu, Thank you for the review. On Thu, Mar 28, 2024 at 8:13 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > > > > On 28.03.2024 10:02, claudiu beznea wrote: > > Hi, Prabhakar, > > > > On 27.03.2024 00:28, Prabhakar wrote: > >> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >> > >> On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. > >> However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls > >> writing to both PFC and PMC registers. To accommodate these differences > >> across SoC variants, introduce set_pfc_mode() and pm_set_pfc() function > >> pointers. > > > > I think the overall code can be simplified if you add 1 function that does > > the lock/unlock for PWPR. See patch 13. > > I meant to say one function for lock and one for unlock. > I agree, let me remodel it that way. Cheers, Prabhakar
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 705372faaeff..4cdebdbd8a04 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -246,6 +246,8 @@ struct rzg2l_variable_pin_cfg { u32 pin:3; }; +struct rzg2l_pinctrl; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -256,6 +258,8 @@ struct rzg2l_pinctrl_data { const struct rzg2l_hwcfg *hwcfg; const struct rzg2l_variable_pin_cfg *variable_pin_cfg; unsigned int n_variable_pin_cfg; + void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); + void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); }; /** @@ -526,7 +530,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); + pctrl->data->set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; @@ -2607,7 +2611,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); } - rzg2l_pinctrl_pm_setup_pfc(pctrl); + pctrl->data->pm_set_pfc(pctrl); rzg2l_pinctrl_pm_setup_regs(pctrl, false); rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); rzg2l_gpio_irq_restore(pctrl); @@ -2672,6 +2676,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .variable_pin_cfg = r9a07g043f_variable_pin_cfg, .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), #endif + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2683,6 +2689,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), .hwcfg = &rzg2l_hwcfg, + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2693,6 +2701,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), .hwcfg = &rzg3s_hwcfg, + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = {