| Message ID | 20240307140728.190184-1-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | clk: renesas: rzg2l: Add support for power domains | expand |
Hi Claudiu, On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra > power when clocks are disabled by activating module standby. This is done > through MSTOP-specific registers that are part of CPG. Each individual > module has one or more bits associated with one MSTOP register (see table > "Registers for Module Standby Mode" from HW manuals). Hardware manual > associates modules' clocks with one or more MSTOP bits. There are 3 > mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW > manuals): > > case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) > case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) > case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) > > Case 3 has been currently identified on RZ/V2L for the VCPL4 module. > > To cover all three cases, the individual platform drivers will provide to > clock driver MSTOP register offset and associated bits in this register > as a bitmask and the clock driver will apply this bitmask to proper > MSTOP register. > > Apart from MSTOP support, RZ/G3S can save more power by powering down the > individual IPs (after MSTOP has been set) if proper bits in > CPG_PWRDN_IP{1,2} registers are set. > > The MSTOP and IP power down support were implemented through power > domains. Platform-specific clock drivers will register an array of > type struct rzg2l_cpg_pm_domain_init_data, which will be used to > instantiate properly the power domains. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - called pm_genpd_init() with proper value for is_off argument > - fixed typos > - used flexible array for struct rzg2l_cpg_pm_domains::domains member > - moved genpd member of struct rzg2l_cpg_pd at the beginning of struct > - didn't initialize the parent variable in rzg2l_cpg_add_pm_domains() > as it is already initialized in the for block from > rzg2l_cpg_add_pm_domains() and that initialization should be enough > - dropped RZG2L_PD_F_PARENT flag > - used datasheet naming for all MSTOP registers > - added all MSTOP registers to rzg2l-cpg.h > - reworked the code that initializes the register offset and bits for domains > - dropped MSTOP*(), PWRDN*() macros and introduced struct rzg2l_cpg_reg_conf > and DEF_REG_CONF() for domain description > - constified the 1st argument of rzg2l_cpg_pm_domain_xlate() > - used dev instead of priv->dev where possible > - dropped RZG2L_PD_F_PARENT > - added RZG2L_PD_F_NONE for better description of domains in platform > specific clock drivers Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Change in v2: > - used DEF_REG_CONF() to describe register offests and bits > - updated MSTOP bitmask for ddr domain > - updated MSTOP config for oftde_ddr > - kept the same description for gic as the CPG_BUS_ACPU_MSTOP register > documentation in the latest HW manual version is wrong and it will be > fixed; proper description for GIC is located in "Registers for Module > Standby Mode" table > - haven't added watchdog domain (was missing in v1, too, by mistake) as > the watchdog restart handler will fail w/o patch [1]; with this pm domain > support the watchdog will fail to probe; not sure what is the best > option until [1] will be integrated > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240228083253.2640997-10-claudiu.beznea.uj@bp.renesas.com I guess we'll have to wait until that dependency is integrated, or use an immutable branch? Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Thu, Mar 7, 2024 at 3:08 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Update CPG #power-domain-cells = <1> and move all the IPs to be part of the > IP specific power domain as the driver has been modified to support > multiple power domains. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - used proper domain ID for IA55 interrupt controller Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Claudiu, On Thu, Mar 7, 2024 at 3:08 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > The RZG2L_PD_F_CONSOLE is used by the rzg2l-cpg driver to check if the > SCIF domain need to be powered off in suspend. This is necessary when > no_console_suspend is available in bootargs as we want to still see > output on console, thus scif0 domain should remain powered on. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a08g045-cpg.c > +++ b/drivers/clk/renesas/r9a08g045-cpg.c > @@ -293,7 +293,7 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { > DEF_PD("scif0", R9A08G045_PD_SCIF0, > DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), > DEF_REG_CONF(0, 0), > - RZG2L_PD_F_NONE), > + RZG2L_PD_F_CONSOLE), This is not really correct: if SCIF0 is used as the console depends on the use case, i.e. on chosen/stdout-path. So this flag should be set at run-time. You can check the power-domains property of the node pointed to by of_stdout to find the PM Domain that holds the console, cfr. drivers/pmdomain/renesas/rmobile-sysc.c. > }; > > const struct rzg2l_cpg_info r9a08g045_cpg_info = { Gr{oetje,eeting}s, Geert
Hi, Geert, On 14.03.2024 18:06, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Thu, Mar 7, 2024 at 3:08 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> The RZG2L_PD_F_CONSOLE is used by the rzg2l-cpg driver to check if the >> SCIF domain need to be powered off in suspend. This is necessary when >> no_console_suspend is available in bootargs as we want to still see >> output on console, thus scif0 domain should remain powered on. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Thanks for your patch! > >> --- a/drivers/clk/renesas/r9a08g045-cpg.c >> +++ b/drivers/clk/renesas/r9a08g045-cpg.c >> @@ -293,7 +293,7 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { >> DEF_PD("scif0", R9A08G045_PD_SCIF0, >> DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), >> DEF_REG_CONF(0, 0), >> - RZG2L_PD_F_NONE), >> + RZG2L_PD_F_CONSOLE), > > This is not really correct: if SCIF0 is used as the console depends on the > use case, i.e. on chosen/stdout-path. > So this flag should be set at run-time. You can check the power-domains > property of the node pointed to by of_stdout to find the PM Domain that > holds the console, cfr. drivers/pmdomain/renesas/rmobile-sysc.c. OK, I'll double check. Thank you, Claudiu Beznea > >> }; >> >> const struct rzg2l_cpg_info r9a08g045_cpg_info = { > > Gr{oetje,eeting}s, > > Geert >
Hi Claudiu, On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > RZ/G3S supports deep sleep states that it can reach with the help of the > TF-A. > > RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while > Linux is running. These domains are initialized (and powered on) when > clock driver is probed. > > As the TF-A takes control at the very last(suspend)/first(resume) > phase of configuring the deep sleep state, it can do it's own settings on > power domains. > > Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which > powers on the always-on domains and rzg2l_cpg_complete() which activates > the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. > > Along with it, added the suspend_check member to the RZ/G2L power domain > data structure whose purpose is to checks if a domain can be powered off > while the system is going to suspend. This is necessary for the serial > console domain which needs to be powered on if no_console_suspend is > available in bootargs. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - none; this patch is new Thanks for your patch! > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -1700,6 +1719,8 @@ static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) > } else { > pd->genpd.power_on = rzg2l_cpg_power_on; > pd->genpd.power_off = rzg2l_cpg_power_off; > + if (flags & RZG2L_PD_F_CONSOLE) I think this should be replaced by some dynamic check, cfr. my comments on PATCH 9/10. > + pd->suspend_check = rzg2l_pd_suspend_check_console; > governor = &simple_qos_governor; > } > > @@ -1890,9 +1911,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) > if (error) > return error; > > + dev_set_drvdata(dev, priv); > + > return 0; > } > > +static int rzg2l_cpg_resume(struct device *dev) > +{ > + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); > + const struct rzg2l_cpg_info *info = priv->info; > + > + /* Power on always ON domains. */ > + for (unsigned int i = 0; i < info->num_pm_domains; i++) { > + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { If you would check "priv-domains[i].flags & GENPD_FLAG_ALWAYS_ON" instead, I think you can make r9a08g045_pm_domains[] __initconst. You may need to make a copy of the name for pd->genpd.name, though. > + int ret = rzg2l_cpg_power_on(priv->domains[i]); I assume you are sure none of these domains are enabled by TF/A after system resume, or by the pmdomain core code? Gr{oetje,eeting}s, Geert
Hi, Geert, Sorry for replying that late to this one. On 18.03.2024 18:48, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> RZ/G3S supports deep sleep states that it can reach with the help of the >> TF-A. >> >> RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while >> Linux is running. These domains are initialized (and powered on) when >> clock driver is probed. >> >> As the TF-A takes control at the very last(suspend)/first(resume) >> phase of configuring the deep sleep state, it can do it's own settings on >> power domains. >> >> Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which >> powers on the always-on domains and rzg2l_cpg_complete() which activates >> the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. >> >> Along with it, added the suspend_check member to the RZ/G2L power domain >> data structure whose purpose is to checks if a domain can be powered off >> while the system is going to suspend. This is necessary for the serial >> console domain which needs to be powered on if no_console_suspend is >> available in bootargs. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> >> Changes in v2: >> - none; this patch is new > > Thanks for your patch! > >> --- a/drivers/clk/renesas/rzg2l-cpg.c >> +++ b/drivers/clk/renesas/rzg2l-cpg.c >> @@ -1700,6 +1719,8 @@ static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) >> } else { >> pd->genpd.power_on = rzg2l_cpg_power_on; >> pd->genpd.power_off = rzg2l_cpg_power_off; >> + if (flags & RZG2L_PD_F_CONSOLE) > > I think this should be replaced by some dynamic check, cfr. my comments > on PATCH 9/10. I agree. > >> + pd->suspend_check = rzg2l_pd_suspend_check_console; >> governor = &simple_qos_governor; >> } >> > >> @@ -1890,9 +1911,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) >> if (error) >> return error; >> >> + dev_set_drvdata(dev, priv); >> + >> return 0; >> } >> >> +static int rzg2l_cpg_resume(struct device *dev) >> +{ >> + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); >> + const struct rzg2l_cpg_info *info = priv->info; >> + >> + /* Power on always ON domains. */ >> + for (unsigned int i = 0; i < info->num_pm_domains; i++) { >> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { > > If you would check "priv-domains[i].flags & GENPD_FLAG_ALWAYS_ON" > instead, I think you can make r9a08g045_pm_domains[] __initconst. > You may need to make a copy of the name for pd->genpd.name, though. I wanted to avoid this copy. > >> + int ret = rzg2l_cpg_power_on(priv->domains[i]); > > I assume you are sure none of these domains are enabled by TF/A after > system resume, or by the pmdomain core code? Out of TF-A the MSTOP and PWRDN bits for these ones are set and setting CPG_PWRDN_MSTOP though rzg2l_cpg_complete() leads to system being blocked. It is the same as in booting case exlained in cover letter. "the DDR, TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due to the following lines of code from patch 6/10. + /* Prepare for power down the BUSes in power down mode. */ + if (info->pm_domain_pwrdn_mstop) + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); Domain IDs were added to all SoC specific bindings. " The PM domain core code doesn't touch these domains while resuming as of my checkings. Thank you, Claudiu Beznea > > Gr{oetje,eeting}s, > > Geert >
Hi, Geert, On 14.03.2024 18:01, Geert Uytterhoeven wrote: > On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> >> Change in v2: >> - used DEF_REG_CONF() to describe register offests and bits >> - updated MSTOP bitmask for ddr domain >> - updated MSTOP config for oftde_ddr >> - kept the same description for gic as the CPG_BUS_ACPU_MSTOP register >> documentation in the latest HW manual version is wrong and it will be >> fixed; proper description for GIC is located in "Registers for Module >> Standby Mode" table >> - haven't added watchdog domain (was missing in v1, too, by mistake) as >> the watchdog restart handler will fail w/o patch [1]; with this pm domain >> support the watchdog will fail to probe; not sure what is the best >> option until [1] will be integrated >> >> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240228083253.2640997-10-claudiu.beznea.uj@bp.renesas.com > > I guess we'll have to wait until that dependency is integrated, I opt for this option to not break the reset support currently integrated. I don't have any feedback from maintainers yet on [1], though. I don't know how long it will take. Thank you, Claudiu Beznea > or use an immutable branch? > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
On Thu, 7 Mar 2024 at 15:10, Claudiu <claudiu.beznea@tuxon.dev> wrote: > > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > RZ/G3S supports deep sleep states that it can reach with the help of the > TF-A. > > RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while > Linux is running. These domains are initialized (and powered on) when > clock driver is probed. > > As the TF-A takes control at the very last(suspend)/first(resume) > phase of configuring the deep sleep state, it can do it's own settings on > power domains. For my understanding, can you please elaborate on this part a bit. What does the "last suspend/resume phase" mean, more exactly, here? > > Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which > powers on the always-on domains and rzg2l_cpg_complete() which activates > the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. > > Along with it, added the suspend_check member to the RZ/G2L power domain > data structure whose purpose is to checks if a domain can be powered off > while the system is going to suspend. This is necessary for the serial > console domain which needs to be powered on if no_console_suspend is > available in bootargs. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - none; this patch is new > > drivers/clk/renesas/rzg2l-cpg.c | 66 ++++++++++++++++++++++++++++++--- > drivers/clk/renesas/rzg2l-cpg.h | 1 + > 2 files changed, 62 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > index b36700f4a9f5..b18af227177e 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -15,6 +15,7 @@ > #include <linux/clk.h> > #include <linux/clk-provider.h> > #include <linux/clk/renesas.h> > +#include <linux/console.h> > #include <linux/delay.h> > #include <linux/device.h> > #include <linux/init.h> > @@ -139,6 +140,7 @@ struct rzg2l_pll5_mux_dsi_div_param { > * @num_resets: Number of Module Resets in info->resets[] > * @last_dt_core_clk: ID of the last Core Clock exported to DT > * @info: Pointer to platform data > + * @domains: generic PM domains > * @mux_dsi_div_params: pll5 mux and dsi div parameters > */ > struct rzg2l_cpg_priv { > @@ -155,6 +157,8 @@ struct rzg2l_cpg_priv { > > const struct rzg2l_cpg_info *info; > > + struct generic_pm_domain **domains; > + > struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; > }; > > @@ -1570,12 +1574,14 @@ struct rzg2l_cpg_pm_domains { > * struct rzg2l_cpg_pd - RZ/G2L power domain data structure > * @genpd: generic PM domain > * @priv: pointer to CPG private data structure > + * @suspend_check: check if domain could be powered off in suspend > * @conf: CPG PM domain configuration info > * @id: RZ/G2L power domain ID > */ > struct rzg2l_cpg_pd { > struct generic_pm_domain genpd; > struct rzg2l_cpg_priv *priv; > + int (*suspend_check)(void); > struct rzg2l_cpg_pm_domain_conf conf; > u16 id; > }; > @@ -1676,6 +1682,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) > struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn; > struct rzg2l_cpg_priv *priv = pd->priv; > > + if (pd->suspend_check) { > + int ret = pd->suspend_check(); > + > + if (ret) > + return ret; > + } > + This should not be needed at all, I think. Instead, genpd should be able to take the correct decision during system-wide suspend and simply avoid calling the ->power_off() callback, when that is needed. If I understand correctly, GENPD_FLAG_ACTIVE_WAKEUP is set for the genpd in question. The only remaining thing would then be to let the console driver, during system suspend, check whether "console_suspend_enabled" is set and then call device_set_awake_path() for its device. In this way, genpd should then keep the corresponding PM domain powered-on. > /* Set MSTOP. */ > if (mstop.mask) > writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off); > @@ -1687,8 +1700,14 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) > return 0; > } > > -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) > +static int rzg2l_pd_suspend_check_console(void) > { > + return console_suspend_enabled ? 0 : -EBUSY; > +} > + > +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 flags) > +{ > + bool always_on = !!(flags & RZG2L_PD_F_ALWAYS_ON); > struct dev_power_governor *governor; > > pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; > @@ -1700,6 +1719,8 @@ static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) > } else { > pd->genpd.power_on = rzg2l_cpg_power_on; > pd->genpd.power_off = rzg2l_cpg_power_off; > + if (flags & RZG2L_PD_F_CONSOLE) > + pd->suspend_check = rzg2l_pd_suspend_check_console; > governor = &simple_qos_governor; > } > > @@ -1719,7 +1740,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) > > pd->genpd.name = np->name; > pd->priv = priv; > - ret = rzg2l_cpg_pd_setup(pd, true); > + ret = rzg2l_cpg_pd_setup(pd, RZG2L_PD_F_ALWAYS_ON); > if (ret) > return ret; > > @@ -1778,13 +1799,13 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) > domains->onecell_data.domains = domains->domains; > domains->onecell_data.num_domains = info->num_pm_domains; > domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate; > + priv->domains = domains->domains; > > ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data); > if (ret) > return ret; > > for (unsigned int i = 0; i < info->num_pm_domains; i++) { > - bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); > struct rzg2l_cpg_pd *pd; > > pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); > @@ -1796,11 +1817,11 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) > pd->id = info->pm_domains[i].id; > pd->priv = priv; > > - ret = rzg2l_cpg_pd_setup(pd, always_on); > + ret = rzg2l_cpg_pd_setup(pd, info->pm_domains[i].flags); > if (ret) > return ret; > > - if (always_on) { > + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { > ret = rzg2l_cpg_power_on(&pd->genpd); > if (ret) > return ret; > @@ -1890,9 +1911,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) > if (error) > return error; > > + dev_set_drvdata(dev, priv); > + > return 0; > } > > +static int rzg2l_cpg_resume(struct device *dev) > +{ > + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); > + const struct rzg2l_cpg_info *info = priv->info; > + > + /* Power on always ON domains. */ > + for (unsigned int i = 0; i < info->num_pm_domains; i++) { > + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { > + int ret = rzg2l_cpg_power_on(priv->domains[i]); > + > + if (ret) > + return ret; > + } > + } I don't quite understand why this is needed? Is always-on PM domains being powered-off during system wide suspend, so you need to power them on again? > + > + return 0; > +} > + > +static void rzg2l_cpg_complete(struct device *dev) > +{ > + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); > + > + /* Prepare for power down the BUSes in power down mode. */ > + if (priv->info->pm_domain_pwrdn_mstop) > + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); > +} > + > +static const struct dev_pm_ops rzg2l_cpg_pm_ops = { > + NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume) > + .complete = rzg2l_cpg_complete, > +}; > + > static const struct of_device_id rzg2l_cpg_match[] = { > #ifdef CONFIG_CLK_R9A07G043 > { > @@ -1931,6 +1986,7 @@ static struct platform_driver rzg2l_cpg_driver = { > .driver = { > .name = "rzg2l-cpg", > .of_match_table = rzg2l_cpg_match, > + .pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops), > }, > }; > > diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h > index d9a7357c4873..abff85644270 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.h > +++ b/drivers/clk/renesas/rzg2l-cpg.h > @@ -301,6 +301,7 @@ struct rzg2l_cpg_pm_domain_init_data { > > /* Power domain flags. */ > #define RZG2L_PD_F_ALWAYS_ON BIT(0) > +#define RZG2L_PD_F_CONSOLE BIT(1) > #define RZG2L_PD_F_NONE (0) > Kind regards Uffe
Hi, Ulf, On 16.04.2024 15:07, Ulf Hansson wrote: > On Thu, 7 Mar 2024 at 15:10, Claudiu <claudiu.beznea@tuxon.dev> wrote: >> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> RZ/G3S supports deep sleep states that it can reach with the help of the >> TF-A. >> >> RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while >> Linux is running. These domains are initialized (and powered on) when >> clock driver is probed. >> >> As the TF-A takes control at the very last(suspend)/first(resume) >> phase of configuring the deep sleep state, it can do it's own settings on >> power domains. > > For my understanding, can you please elaborate on this part a bit. > What does the "last suspend/resume phase" mean, more exactly, here? The RZ/G3S SoC support a power saving mode where most of the SoC parts are turned off and the system RAM is switched to retention mode. This is done with the help of TF-A. The handshake b/w Linux and TF-A is done though the drivers/firmware/psci/psci.c driver. After Linux finishes the execution of suspend code the control is taken by TF-A. TF-A does the final settings on the system (e.g. switching the RAM to retention mode) and power off most of the SoC parts. By the last phase of the suspend I'm referring to the TF-A doing the final adjustments for the system to switch to this power saving mode. When resuming, as the TF-A is the 1st one being executed on the system (this is what I called above the 1st phase of the resume), TF-A moves the DDR out of retention mode, reconfigure basic IPs (like in boot case as most of the SoC parts were powered off) and then give the control to Linux which will execute the resume code. > >> >> Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which >> powers on the always-on domains and rzg2l_cpg_complete() which activates >> the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. >> >> Along with it, added the suspend_check member to the RZ/G2L power domain >> data structure whose purpose is to checks if a domain can be powered off >> while the system is going to suspend. This is necessary for the serial >> console domain which needs to be powered on if no_console_suspend is >> available in bootargs. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> >> Changes in v2: >> - none; this patch is new >> >> drivers/clk/renesas/rzg2l-cpg.c | 66 ++++++++++++++++++++++++++++++--- >> drivers/clk/renesas/rzg2l-cpg.h | 1 + >> 2 files changed, 62 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c >> index b36700f4a9f5..b18af227177e 100644 >> --- a/drivers/clk/renesas/rzg2l-cpg.c >> +++ b/drivers/clk/renesas/rzg2l-cpg.c >> @@ -15,6 +15,7 @@ >> #include <linux/clk.h> >> #include <linux/clk-provider.h> >> #include <linux/clk/renesas.h> >> +#include <linux/console.h> >> #include <linux/delay.h> >> #include <linux/device.h> >> #include <linux/init.h> >> @@ -139,6 +140,7 @@ struct rzg2l_pll5_mux_dsi_div_param { >> * @num_resets: Number of Module Resets in info->resets[] >> * @last_dt_core_clk: ID of the last Core Clock exported to DT >> * @info: Pointer to platform data >> + * @domains: generic PM domains >> * @mux_dsi_div_params: pll5 mux and dsi div parameters >> */ >> struct rzg2l_cpg_priv { >> @@ -155,6 +157,8 @@ struct rzg2l_cpg_priv { >> >> const struct rzg2l_cpg_info *info; >> >> + struct generic_pm_domain **domains; >> + >> struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; >> }; >> >> @@ -1570,12 +1574,14 @@ struct rzg2l_cpg_pm_domains { >> * struct rzg2l_cpg_pd - RZ/G2L power domain data structure >> * @genpd: generic PM domain >> * @priv: pointer to CPG private data structure >> + * @suspend_check: check if domain could be powered off in suspend >> * @conf: CPG PM domain configuration info >> * @id: RZ/G2L power domain ID >> */ >> struct rzg2l_cpg_pd { >> struct generic_pm_domain genpd; >> struct rzg2l_cpg_priv *priv; >> + int (*suspend_check)(void); >> struct rzg2l_cpg_pm_domain_conf conf; >> u16 id; >> }; >> @@ -1676,6 +1682,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) >> struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn; >> struct rzg2l_cpg_priv *priv = pd->priv; >> >> + if (pd->suspend_check) { >> + int ret = pd->suspend_check(); >> + >> + if (ret) >> + return ret; >> + } >> + > > This should not be needed at all, I think. > > Instead, genpd should be able to take the correct decision during > system-wide suspend and simply avoid calling the ->power_off() > callback, when that is needed. > > If I understand correctly, GENPD_FLAG_ACTIVE_WAKEUP is set for the > genpd in question. The only remaining thing would then be to let the > console driver, during system suspend, check whether > "console_suspend_enabled" is set and then call device_set_awake_path() > for its device. In this way, genpd should then keep the corresponding > PM domain powered-on. You're right! I've checked it and all good w/o ->suspend_check() if device_set_wakeup_path() is called for the console driver. I'll send an update for it. > >> /* Set MSTOP. */ >> if (mstop.mask) >> writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off); >> @@ -1687,8 +1700,14 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) >> return 0; >> } >> >> -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) >> +static int rzg2l_pd_suspend_check_console(void) >> { >> + return console_suspend_enabled ? 0 : -EBUSY; >> +} >> + >> +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 flags) >> +{ >> + bool always_on = !!(flags & RZG2L_PD_F_ALWAYS_ON); >> struct dev_power_governor *governor; >> >> pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; >> @@ -1700,6 +1719,8 @@ static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) >> } else { >> pd->genpd.power_on = rzg2l_cpg_power_on; >> pd->genpd.power_off = rzg2l_cpg_power_off; >> + if (flags & RZG2L_PD_F_CONSOLE) >> + pd->suspend_check = rzg2l_pd_suspend_check_console; >> governor = &simple_qos_governor; >> } >> >> @@ -1719,7 +1740,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) >> >> pd->genpd.name = np->name; >> pd->priv = priv; >> - ret = rzg2l_cpg_pd_setup(pd, true); >> + ret = rzg2l_cpg_pd_setup(pd, RZG2L_PD_F_ALWAYS_ON); >> if (ret) >> return ret; >> >> @@ -1778,13 +1799,13 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) >> domains->onecell_data.domains = domains->domains; >> domains->onecell_data.num_domains = info->num_pm_domains; >> domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate; >> + priv->domains = domains->domains; >> >> ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data); >> if (ret) >> return ret; >> >> for (unsigned int i = 0; i < info->num_pm_domains; i++) { >> - bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); >> struct rzg2l_cpg_pd *pd; >> >> pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); >> @@ -1796,11 +1817,11 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) >> pd->id = info->pm_domains[i].id; >> pd->priv = priv; >> >> - ret = rzg2l_cpg_pd_setup(pd, always_on); >> + ret = rzg2l_cpg_pd_setup(pd, info->pm_domains[i].flags); >> if (ret) >> return ret; >> >> - if (always_on) { >> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { >> ret = rzg2l_cpg_power_on(&pd->genpd); >> if (ret) >> return ret; >> @@ -1890,9 +1911,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) >> if (error) >> return error; >> >> + dev_set_drvdata(dev, priv); >> + >> return 0; >> } >> >> +static int rzg2l_cpg_resume(struct device *dev) >> +{ >> + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); >> + const struct rzg2l_cpg_info *info = priv->info; >> + >> + /* Power on always ON domains. */ >> + for (unsigned int i = 0; i < info->num_pm_domains; i++) { >> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { >> + int ret = rzg2l_cpg_power_on(priv->domains[i]); >> + >> + if (ret) >> + return ret; >> + } >> + } > > I don't quite understand why this is needed? Is always-on PM domains > being powered-off during system wide suspend, so you need to power > them on again? Yes, as power to most of the system parts is cut off during sytem suspend (and DDR is kept in retention mode) and the resume is almost like a cold boot where the TF-A does basic re-initialization and then pass execution to Linux resume code. Thank you, Claudiu Beznea > >> + >> + return 0; >> +} >> + >> +static void rzg2l_cpg_complete(struct device *dev) >> +{ >> + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); >> + >> + /* Prepare for power down the BUSes in power down mode. */ >> + if (priv->info->pm_domain_pwrdn_mstop) >> + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); >> +} >> + >> +static const struct dev_pm_ops rzg2l_cpg_pm_ops = { >> + NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume) >> + .complete = rzg2l_cpg_complete, >> +}; >> + >> static const struct of_device_id rzg2l_cpg_match[] = { >> #ifdef CONFIG_CLK_R9A07G043 >> { >> @@ -1931,6 +1986,7 @@ static struct platform_driver rzg2l_cpg_driver = { >> .driver = { >> .name = "rzg2l-cpg", >> .of_match_table = rzg2l_cpg_match, >> + .pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops), >> }, >> }; >> >> diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h >> index d9a7357c4873..abff85644270 100644 >> --- a/drivers/clk/renesas/rzg2l-cpg.h >> +++ b/drivers/clk/renesas/rzg2l-cpg.h >> @@ -301,6 +301,7 @@ struct rzg2l_cpg_pm_domain_init_data { >> >> /* Power domain flags. */ >> #define RZG2L_PD_F_ALWAYS_ON BIT(0) >> +#define RZG2L_PD_F_CONSOLE BIT(1) >> #define RZG2L_PD_F_NONE (0) >> > > Kind regards > Uffe
On Wed, 17 Apr 2024 at 10:05, claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > > Hi, Ulf, > > On 16.04.2024 15:07, Ulf Hansson wrote: > > On Thu, 7 Mar 2024 at 15:10, Claudiu <claudiu.beznea@tuxon.dev> wrote: > >> > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> > >> RZ/G3S supports deep sleep states that it can reach with the help of the > >> TF-A. > >> > >> RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while > >> Linux is running. These domains are initialized (and powered on) when > >> clock driver is probed. > >> > >> As the TF-A takes control at the very last(suspend)/first(resume) > >> phase of configuring the deep sleep state, it can do it's own settings on > >> power domains. > > > > For my understanding, can you please elaborate on this part a bit. > > What does the "last suspend/resume phase" mean, more exactly, here? > > The RZ/G3S SoC support a power saving mode where most of the SoC parts are > turned off and the system RAM is switched to retention mode. This is done > with the help of TF-A. The handshake b/w Linux and TF-A is done though the > drivers/firmware/psci/psci.c driver. > > After Linux finishes the execution of suspend code the control is taken by > TF-A. TF-A does the final settings on the system (e.g. switching the RAM to > retention mode) and power off most of the SoC parts. > > By the last phase of the suspend I'm referring to the TF-A doing the final > adjustments for the system to switch to this power saving mode. > > When resuming, as the TF-A is the 1st one being executed on the system > (this is what I called above the 1st phase of the resume), TF-A moves the > DDR out of retention mode, reconfigure basic IPs (like in boot case as most > of the SoC parts were powered off) and then give the control to Linux which > will execute the resume code. Alright, thanks for clarifying! This makes sense to me now! > > > > > >> > >> Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which > >> powers on the always-on domains and rzg2l_cpg_complete() which activates > >> the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. > >> > >> Along with it, added the suspend_check member to the RZ/G2L power domain > >> data structure whose purpose is to checks if a domain can be powered off > >> while the system is going to suspend. This is necessary for the serial > >> console domain which needs to be powered on if no_console_suspend is > >> available in bootargs. > >> > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> --- > >> > >> Changes in v2: > >> - none; this patch is new > >> > >> drivers/clk/renesas/rzg2l-cpg.c | 66 ++++++++++++++++++++++++++++++--- > >> drivers/clk/renesas/rzg2l-cpg.h | 1 + > >> 2 files changed, 62 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > >> index b36700f4a9f5..b18af227177e 100644 > >> --- a/drivers/clk/renesas/rzg2l-cpg.c > >> +++ b/drivers/clk/renesas/rzg2l-cpg.c > >> @@ -15,6 +15,7 @@ > >> #include <linux/clk.h> > >> #include <linux/clk-provider.h> > >> #include <linux/clk/renesas.h> > >> +#include <linux/console.h> > >> #include <linux/delay.h> > >> #include <linux/device.h> > >> #include <linux/init.h> > >> @@ -139,6 +140,7 @@ struct rzg2l_pll5_mux_dsi_div_param { > >> * @num_resets: Number of Module Resets in info->resets[] > >> * @last_dt_core_clk: ID of the last Core Clock exported to DT > >> * @info: Pointer to platform data > >> + * @domains: generic PM domains > >> * @mux_dsi_div_params: pll5 mux and dsi div parameters > >> */ > >> struct rzg2l_cpg_priv { > >> @@ -155,6 +157,8 @@ struct rzg2l_cpg_priv { > >> > >> const struct rzg2l_cpg_info *info; > >> > >> + struct generic_pm_domain **domains; > >> + > >> struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; > >> }; > >> > >> @@ -1570,12 +1574,14 @@ struct rzg2l_cpg_pm_domains { > >> * struct rzg2l_cpg_pd - RZ/G2L power domain data structure > >> * @genpd: generic PM domain > >> * @priv: pointer to CPG private data structure > >> + * @suspend_check: check if domain could be powered off in suspend > >> * @conf: CPG PM domain configuration info > >> * @id: RZ/G2L power domain ID > >> */ > >> struct rzg2l_cpg_pd { > >> struct generic_pm_domain genpd; > >> struct rzg2l_cpg_priv *priv; > >> + int (*suspend_check)(void); > >> struct rzg2l_cpg_pm_domain_conf conf; > >> u16 id; > >> }; > >> @@ -1676,6 +1682,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) > >> struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn; > >> struct rzg2l_cpg_priv *priv = pd->priv; > >> > >> + if (pd->suspend_check) { > >> + int ret = pd->suspend_check(); > >> + > >> + if (ret) > >> + return ret; > >> + } > >> + > > > > This should not be needed at all, I think. > > > > Instead, genpd should be able to take the correct decision during > > system-wide suspend and simply avoid calling the ->power_off() > > callback, when that is needed. > > > > If I understand correctly, GENPD_FLAG_ACTIVE_WAKEUP is set for the > > genpd in question. The only remaining thing would then be to let the > > console driver, during system suspend, check whether > > "console_suspend_enabled" is set and then call device_set_awake_path() > > for its device. In this way, genpd should then keep the corresponding > > PM domain powered-on. > > You're right! I've checked it and all good w/o ->suspend_check() if > device_set_wakeup_path() is called for the console driver. > > I'll send an update for it. Great! Please keep me posted on the entire series for next version. I will try to continue to help review this. > > > > >> /* Set MSTOP. */ > >> if (mstop.mask) > >> writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off); > >> @@ -1687,8 +1700,14 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) > >> return 0; > >> } > >> > >> -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) > >> +static int rzg2l_pd_suspend_check_console(void) > >> { > >> + return console_suspend_enabled ? 0 : -EBUSY; > >> +} > >> + > >> +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 flags) > >> +{ > >> + bool always_on = !!(flags & RZG2L_PD_F_ALWAYS_ON); > >> struct dev_power_governor *governor; > >> > >> pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; > >> @@ -1700,6 +1719,8 @@ static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) > >> } else { > >> pd->genpd.power_on = rzg2l_cpg_power_on; > >> pd->genpd.power_off = rzg2l_cpg_power_off; > >> + if (flags & RZG2L_PD_F_CONSOLE) > >> + pd->suspend_check = rzg2l_pd_suspend_check_console; > >> governor = &simple_qos_governor; > >> } > >> > >> @@ -1719,7 +1740,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) > >> > >> pd->genpd.name = np->name; > >> pd->priv = priv; > >> - ret = rzg2l_cpg_pd_setup(pd, true); > >> + ret = rzg2l_cpg_pd_setup(pd, RZG2L_PD_F_ALWAYS_ON); > >> if (ret) > >> return ret; > >> > >> @@ -1778,13 +1799,13 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) > >> domains->onecell_data.domains = domains->domains; > >> domains->onecell_data.num_domains = info->num_pm_domains; > >> domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate; > >> + priv->domains = domains->domains; > >> > >> ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data); > >> if (ret) > >> return ret; > >> > >> for (unsigned int i = 0; i < info->num_pm_domains; i++) { > >> - bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); > >> struct rzg2l_cpg_pd *pd; > >> > >> pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); > >> @@ -1796,11 +1817,11 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) > >> pd->id = info->pm_domains[i].id; > >> pd->priv = priv; > >> > >> - ret = rzg2l_cpg_pd_setup(pd, always_on); > >> + ret = rzg2l_cpg_pd_setup(pd, info->pm_domains[i].flags); > >> if (ret) > >> return ret; > >> > >> - if (always_on) { > >> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { > >> ret = rzg2l_cpg_power_on(&pd->genpd); > >> if (ret) > >> return ret; > >> @@ -1890,9 +1911,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) > >> if (error) > >> return error; > >> > >> + dev_set_drvdata(dev, priv); > >> + > >> return 0; > >> } > >> > >> +static int rzg2l_cpg_resume(struct device *dev) > >> +{ > >> + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); > >> + const struct rzg2l_cpg_info *info = priv->info; > >> + > >> + /* Power on always ON domains. */ > >> + for (unsigned int i = 0; i < info->num_pm_domains; i++) { > >> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { > >> + int ret = rzg2l_cpg_power_on(priv->domains[i]); > >> + > >> + if (ret) > >> + return ret; > >> + } > >> + } > > > > I don't quite understand why this is needed? Is always-on PM domains > > being powered-off during system wide suspend, so you need to power > > them on again? > > Yes, as power to most of the system parts is cut off during sytem suspend > (and DDR is kept in retention mode) and the resume is almost like a cold > boot where the TF-A does basic re-initialization and then pass execution to > Linux resume code. Hmm. If these are really always-on PM domains, why isn't the FW powering them on again then before returning to Linux after a system resume? In a way it sounds to me that they aren't really always-on PM domains, as Linux seems to be capable of turning them on/off too, right? That said, perhaps using GENPD_FLAG_RPM_ALWAYS_ON instead of GENPD_FLAG_ALWAYS_ON for some PM domains can be another way forward? In this way, the ->power_on|off() callbacks can be used to turn on/off the PM domains, but only during system suspend/resume. Would that work? [...] Kind regards Uffe
On 17.04.2024 12:39, Ulf Hansson wrote: > On Wed, 17 Apr 2024 at 10:05, claudiu beznea <claudiu.beznea@tuxon.dev> wrote: >> >> Hi, Ulf, >> >> On 16.04.2024 15:07, Ulf Hansson wrote: >>> On Thu, 7 Mar 2024 at 15:10, Claudiu <claudiu.beznea@tuxon.dev> wrote: >>>> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>>> >>>> RZ/G3S supports deep sleep states that it can reach with the help of the >>>> TF-A. >>>> >>>> RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while >>>> Linux is running. These domains are initialized (and powered on) when >>>> clock driver is probed. >>>> >>>> As the TF-A takes control at the very last(suspend)/first(resume) >>>> phase of configuring the deep sleep state, it can do it's own settings on >>>> power domains. >>> >>> For my understanding, can you please elaborate on this part a bit. >>> What does the "last suspend/resume phase" mean, more exactly, here? >> >> The RZ/G3S SoC support a power saving mode where most of the SoC parts are >> turned off and the system RAM is switched to retention mode. This is done >> with the help of TF-A. The handshake b/w Linux and TF-A is done though the >> drivers/firmware/psci/psci.c driver. >> >> After Linux finishes the execution of suspend code the control is taken by >> TF-A. TF-A does the final settings on the system (e.g. switching the RAM to >> retention mode) and power off most of the SoC parts. >> >> By the last phase of the suspend I'm referring to the TF-A doing the final >> adjustments for the system to switch to this power saving mode. >> >> When resuming, as the TF-A is the 1st one being executed on the system >> (this is what I called above the 1st phase of the resume), TF-A moves the >> DDR out of retention mode, reconfigure basic IPs (like in boot case as most >> of the SoC parts were powered off) and then give the control to Linux which >> will execute the resume code. > > Alright, thanks for clarifying! This makes sense to me now! > >> >> >>> >>>> >>>> Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which >>>> powers on the always-on domains and rzg2l_cpg_complete() which activates >>>> the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. >>>> >>>> Along with it, added the suspend_check member to the RZ/G2L power domain >>>> data structure whose purpose is to checks if a domain can be powered off >>>> while the system is going to suspend. This is necessary for the serial >>>> console domain which needs to be powered on if no_console_suspend is >>>> available in bootargs. >>>> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>>> --- [ ... ] >>>> >>>> +static int rzg2l_cpg_resume(struct device *dev) >>>> +{ >>>> + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); >>>> + const struct rzg2l_cpg_info *info = priv->info; >>>> + >>>> + /* Power on always ON domains. */ >>>> + for (unsigned int i = 0; i < info->num_pm_domains; i++) { >>>> + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { >>>> + int ret = rzg2l_cpg_power_on(priv->domains[i]); >>>> + >>>> + if (ret) >>>> + return ret; >>>> + } >>>> + } >>> >>> I don't quite understand why this is needed? Is always-on PM domains >>> being powered-off during system wide suspend, so you need to power >>> them on again? >> >> Yes, as power to most of the system parts is cut off during sytem suspend >> (and DDR is kept in retention mode) and the resume is almost like a cold >> boot where the TF-A does basic re-initialization and then pass execution to >> Linux resume code. > > Hmm. If these are really always-on PM domains, why isn't the FW > powering them on again then before returning to Linux after a system > resume? I'll try to explain it better. The power domain implementation in this series tries to abstract the control of bus clock (though MSTOP registers) for individual modules available in RZ/G3S SoC. From hardware manual [1]: "The Module Standby Mode is a mode that requests the clock stop of the module specified by the master. The purpose of this mode is to reduce power consumption by stopping unnecessary functions." MSTOP is connected to individual modules as described in this picture: https://paste.pics/726c963c33a506651a4be5f327e2a46d There is also the PWRDN functionality for the modules that are part of the PD_ISOVCC domain. At the time of writing this series there was not much information in hardware manual about PWRDN functionality. The design team has been asked but there is no clear answer ATM if the sequence of using PWRDN in Linux (as proposed in this series) is good or not. I encountered no issues with it while experimenting thus I have kept it. If you prefer I can drop it and return with something afterwards, if any. As I said in the current implementation I also used the PWRDN. The PWRDN is IP specific but takes effect (as of my experiments) when this is executed: + /* Prepare for power down the BUSes in power down mode. */ + if (info->pm_domain_pwrdn_mstop) + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); As of my experiments having CPG_PWRDN_MSTOP.CPG_PWRDN_MSTOP_ENABLE set applies the PWRDN to all the IPs for which PWRDN bit has been set in CPG_PWRDN_IP1 and CPG_PWRD_IP2 registers. This settings are applied in probe after domains are powered (thus PWRDN bits are properly set up for IP supporting it by calling ->power_on()) and at the end of resume (after PWRDN bits are properly setup for IPs supporting it by calling ->power_on()) From my experiments, when returning from suspend (thus after firmware has been executed) the CPG_PWRDN_MSTOP_ENABLE bit at register CPG_PWRDN_MSTOP is zero. We power on the domains in Linux after resuming because of PWRDN functionality and CPG_PWRDN_MSTOP_ENABLE bit at register CPG_PWRDN_MSTOP. > > In a way it sounds to me that they aren't really always-on PM domains, > as Linux seems to be capable of turning them on/off too, right? Yes, Linux has the ability of controlling them by setting MSTOP and PWRDN bits. This is because the IP specific PWRDN functionality takes effect when CPG_PWRDN_MSTOP_ENABLE bit at register CPG_PWRDN_MSTOP is set (as of my experiments). > > That said, perhaps using GENPD_FLAG_RPM_ALWAYS_ON instead of > GENPD_FLAG_ALWAYS_ON for some PM domains can be another way forward? All this is becuase PWRD functionality. Explaining it to you made me consider that it would be better to just drop the PWRDN functionality at the moment until it is fully understood. With it I think we should be able to drop the rzg2l_cpg_power_on() in resume(), at least. What do you think? > In this way, the ->power_on|off() callbacks can be used to turn on/off > the PM domains, but only during system suspend/resume. Would that > work? I need to check it. Thank you for you review, Claudiu Beznea [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250 > > [...] > > Kind regards > Uffe
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Hi, Series adds support for power domains on rzg2l driver. RZ/G2L kind of devices support a functionality called MSTOP (module stop/standby). According to hardware manual the module could be switch to standby after its clocks are disabled. The reverse order of operation should be done when enabling a module (get the module out of standby, enable its clocks etc). In [1] the MSTOP settings were implemented by adding code in driver to attach the MSTOP state to the IP clocks. But it has been proposed to implement it as power domain. The result is this series. Along with MSTOP functionality there is also module power down functionality (which is currently available only on RZ/G3S). This has been also implemented through power domains. The DT bindings were updated with power domain IDs (plain integers that matches the DT with driver data structures). The current DT bindings were updated with module IDs for the modules listed in tables with name "Registers for Module Standby Mode" (see HW manual) exception being RZ/G3S where, due to the power down functionality, the DDR, TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due to the following lines of code from patch 7/17. + /* Prepare for power down the BUSes in power down mode. */ + if (info->pm_domain_pwrdn_mstop) + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); Domain IDs were added to all SoC specific bindings. Thank you, Claudiu Beznea Changes in v2: - addressed review comments - dropped: - dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs - clk: renesas: r9a07g043: Add initial support for power domains - clk: renesas: r9a07g044: Add initial support for power domains - clk: renesas: r9a09g011: Add initial support for power domains - clk: renesas: r9a09g011: Add initial support for power domains - arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1> - arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1> - arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1> - arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1> as suggested in the review process - dropped "arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags" patch as it was integrated - added suspend to RAM support - collected tag [1] https://lore.kernel.org/all/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com/ Claudiu Beznea (10): dt-bindings: clock: r9a07g043-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S clk: renesas: rzg2l: Extend power domain support clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l-cpg: Add suspend/resume support for power domains clk: renesas: r9a08g045: Add the RZG2L_PD_F_CONSOLE flag to scif0 PM domain arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> .../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 +- drivers/clk/renesas/r9a08g045-cpg.c | 61 ++++ drivers/clk/renesas/rzg2l-cpg.c | 267 +++++++++++++++++- drivers/clk/renesas/rzg2l-cpg.h | 78 +++++ include/dt-bindings/clock/r9a07g043-cpg.h | 52 ++++ include/dt-bindings/clock/r9a07g044-cpg.h | 58 ++++ include/dt-bindings/clock/r9a07g054-cpg.h | 58 ++++ include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++ 9 files changed, 658 insertions(+), 24 deletions(-)