| Message ID | 20240125200108.24374-3-ezra@easyb.ch |
|---|---|
| State | Accepted |
| Headers | show |
| Series | mtd: spinand: Resolve GigaDevice/ESMT ID clash | expand |
On 25.01.2024 23:01, Ezra Buehler wrote: > From: Ezra Buehler <ezra.buehler@husqvarnagroup.com> > > According to the datasheets, the ESMT chips in question will return a 5 > byte long identification code where the last 3 bytes are the JEDEC > continuation codes (7Fh). Although, I would have expected 4 continuation > codes as Powerchip Semiconductor (C8h, corresponding to the parameter > page data) is located in bank 5 of the JEDEC database. > > By matching the full 5 bytes we can avoid clashes with GigaDevice NAND > flashes. > > This fix allows the MT7688-based GARDENA smart Gateway to boot again. > > Fixes: aa08bf187f32 ("mtd: spinand: esmt: add support for F50D2G41KA") > Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Tested for F50L1G41LB Reviewed-by: Martin Kurbanov <mmkurbanov@salutedevices.com> Tested-by: Martin Kurbanov <mmkurbanov@salutedevices.com> > --- > drivers/mtd/nand/spi/esmt.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c > index 31c439a557b1..4597a82de23a 100644 > --- a/drivers/mtd/nand/spi/esmt.c > +++ b/drivers/mtd/nand/spi/esmt.c > @@ -104,7 +104,8 @@ static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = { > > static const struct spinand_info esmt_c8_spinand_table[] = { > SPINAND_INFO("F50L1G41LB", > - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), > + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f, > + 0x7f, 0x7f), > NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), > NAND_ECCREQ(1, 512), > SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > @@ -113,7 +114,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { > 0, > SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), > SPINAND_INFO("F50D1G41LB", > - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11), > + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f, > + 0x7f, 0x7f), > NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), > NAND_ECCREQ(1, 512), > SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > @@ -122,7 +124,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { > 0, > SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), > SPINAND_INFO("F50D2G41KA", > - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), > + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51, 0x7f, > + 0x7f, 0x7f), > NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), > NAND_ECCREQ(8, 512), > SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
Hi Martin, > On 26 Jan 2024, at 20:49, Martin Kurbanov <mmkurbanov@salutedevices.com> wrote: > > Tested for F50L1G41LB > > Reviewed-by: Martin Kurbanov <mmkurbanov@salutedevices.com> > Tested-by: Martin Kurbanov <mmkurbanov@salutedevices.com> Thank you very much for your valuable feedback! Cheers, Ezra.
On Thu, 2024-01-25 at 20:01:08 UTC, Ezra Buehler wrote: > From: Ezra Buehler <ezra.buehler@husqvarnagroup.com> > > According to the datasheets, the ESMT chips in question will return a 5 > byte long identification code where the last 3 bytes are the JEDEC > continuation codes (7Fh). Although, I would have expected 4 continuation > codes as Powerchip Semiconductor (C8h, corresponding to the parameter > page data) is located in bank 5 of the JEDEC database. > > By matching the full 5 bytes we can avoid clashes with GigaDevice NAND > flashes. > > This fix allows the MT7688-based GARDENA smart Gateway to boot again. > > Fixes: aa08bf187f32 ("mtd: spinand: esmt: add support for F50D2G41KA") > Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> > Reviewed-by: Martin Kurbanov <mmkurbanov@salutedevices.com> > Tested-by: Martin Kurbanov <mmkurbanov@salutedevices.com> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel
diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index 31c439a557b1..4597a82de23a 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -104,7 +104,8 @@ static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = { static const struct spinand_info esmt_c8_spinand_table[] = { SPINAND_INFO("F50L1G41LB", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -113,7 +114,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { 0, SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), SPINAND_INFO("F50D1G41LB", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -122,7 +124,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { 0, SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), SPINAND_INFO("F50D2G41KA", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants,