| Message ID | cover.1706194617.git.geert+renesas@glider.be |
|---|---|
| Headers | show |
| Series | arm64: renesas: Add R-Car V4M and Gray Hawk Single support | expand |
Hi Geert, Thanks for your patch. On 2024-01-25 16:34:38 +0100, Geert Uytterhoeven wrote: > Currently, all Kconfig symbols for R-Car Gen4 SoCs select the > ARCH_RCAR_GEN3 SoC family symbol, which might confuse the casual reader. > > Fix this by introducing a new SoC family symbol for R-Car Gen4 SoCs. > For now this just selects ARCH_RCAR_GEN3, to avoid duplication, and to > relax dependencies. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > Once "[PATCH] i2c: rcar: Prepare for the advent of ARCH_RCAR_GEN4"[1] > has been applied, ARCH_RCAR_GEN4 can stop selecting ARCH_RCAR_GEN3. > > v2: > - Add Reviewed-by. > > [1] https://lore.kernel.org/r/bf7b105f7d9728ae5cd9fa99d1cdd278d71e7df2.1704723713.git.geert+renesas@glider.be > --- > drivers/soc/renesas/Kconfig | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig > index 1c14be3e46e58ef1..2367385d84b5a17d 100644 > --- a/drivers/soc/renesas/Kconfig > +++ b/drivers/soc/renesas/Kconfig > @@ -38,6 +38,10 @@ config ARCH_RCAR_GEN3 > select SYS_SUPPORTS_SH_CMT > select SYS_SUPPORTS_SH_TMU > > +config ARCH_RCAR_GEN4 > + bool > + select ARCH_RCAR_GEN3 > + > config ARCH_RMOBILE > bool > select PM > @@ -245,7 +249,7 @@ config ARCH_R8A77961 > > config ARCH_R8A779F0 > bool "ARM64 Platform support for R-Car S4-8" > - select ARCH_RCAR_GEN3 > + select ARCH_RCAR_GEN4 > select SYSC_R8A779F0 > help > This enables support for the Renesas R-Car S4-8 SoC. > @@ -266,14 +270,14 @@ config ARCH_R8A77970 > > config ARCH_R8A779A0 > bool "ARM64 Platform support for R-Car V3U" > - select ARCH_RCAR_GEN3 > + select ARCH_RCAR_GEN4 > select SYSC_R8A779A0 > help > This enables support for the Renesas R-Car V3U SoC. > > config ARCH_R8A779G0 > bool "ARM64 Platform support for R-Car V4H" > - select ARCH_RCAR_GEN3 > + select ARCH_RCAR_GEN4 > select SYSC_R8A779G0 > help > This enables support for the Renesas R-Car V4H SoC. > -- > 2.34.1 > >
Hi Geert, Thanks for your work. On 2024-01-25 16:34:39 +0100, Geert Uytterhoeven wrote: > From: Duy Nguyen <duy.nguyen.rh@renesas.com> > > Add support for identifying the R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - Add Reviewed-by. > > Changes compared to the BSP: > - Use lower-case hex for literals in C source code. > --- > drivers/soc/renesas/Kconfig | 7 +++++++ > drivers/soc/renesas/renesas-soc.c | 8 ++++++++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig > index 2367385d84b5a17d..1b8a89ad4fd7e7a3 100644 > --- a/drivers/soc/renesas/Kconfig > +++ b/drivers/soc/renesas/Kconfig > @@ -282,6 +282,13 @@ config ARCH_R8A779G0 > help > This enables support for the Renesas R-Car V4H SoC. > > +config ARCH_R8A779H0 > + bool "ARM64 Platform support for R-Car V4M" > + select ARCH_RCAR_GEN4 > + select SYSC_R8A779H0 > + help > + This enables support for the Renesas R-Car V4M SoC. > + > config ARCH_R8A774C0 > bool "ARM64 Platform support for RZ/G2E" > select ARCH_RCAR_GEN3 > diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c > index 67de980ec4244c41..083f6580cb5dae00 100644 > --- a/drivers/soc/renesas/renesas-soc.c > +++ b/drivers/soc/renesas/renesas-soc.c > @@ -271,6 +271,11 @@ static const struct renesas_soc soc_rcar_v4h __initconst __maybe_unused = { > .id = 0x5c, > }; > > +static const struct renesas_soc soc_rcar_v4m __initconst __maybe_unused = { > + .family = &fam_rcar_gen4, > + .id = 0x5d, > +}; > + > static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { > .family = &fam_shmobile, > .id = 0x37, > @@ -381,6 +386,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { > #ifdef CONFIG_ARCH_R8A779G0 > { .compatible = "renesas,r8a779g0", .data = &soc_rcar_v4h }, > #endif > +#ifdef CONFIG_ARCH_R8A779H0 > + { .compatible = "renesas,r8a779h0", .data = &soc_rcar_v4m }, > +#endif > #ifdef CONFIG_ARCH_R9A07G043 > #ifdef CONFIG_RISCV > { .compatible = "renesas,r9a07g043", .data = &soc_rz_five }, > -- > 2.34.1 > >
Hi Geert, On 2024-01-25 16:34:40 +0100, Geert Uytterhoeven wrote: > From: Duy Nguyen <duy.nguyen.rh@renesas.com> > > Add support for the R-Car V4M (R8A779H0) SoC to the R-Car RST driver. > > Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > Early firmware versions may not enable WDT resets, so you may need to do > s/rcar_rst_gen4/rcar_rst_v3u/ for testing. > > v2: > - Add Reviewed-by. > --- > drivers/soc/renesas/rcar-rst.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c > index 98fd97da6cd4330d..7ba02f3a4a4fbb9f 100644 > --- a/drivers/soc/renesas/rcar-rst.c > +++ b/drivers/soc/renesas/rcar-rst.c > @@ -117,6 +117,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { > { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u }, > { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, > { .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 }, > + { .compatible = "renesas,r8a779h0-rst", .data = &rcar_rst_gen4 }, > { /* sentinel */ } > }; > > -- > 2.34.1 > >
Hi Geert, On 2024-01-25 16:34:36 +0100, Geert Uytterhoeven wrote: > From: Cong Dang <cong.dang.xn@renesas.com> > > Initial CPG support for the R-Car V4M (R8A779H0). > > Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> I have not checked every value in the table but those I have checked looks good. Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - Add vendor-prefix to DT binding definition header file, > - Add missing CP core clock. > > Changes compared to the BSP: > - Merge two patches, > - Fix whitespace in Makefile, > - Rename VIOSCR/VCSCR to VIOSRC/VCSRC, > - Rename "zN" to "zcN" to match documentation, > - Change register bitfield offsets for zc[1-3] from 0 to actual > values, > - Change parent of IMPBSRC/VIOSRC/VCSRC from PLL1_DIV2 to PLL1, > - Add missing SD0H clock, > - Change parent of SD0 from SDSRC to SD0H, > - Fix No newline at end of file. > --- > drivers/clk/renesas/Kconfig | 5 + > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r8a779h0-cpg-mssr.c | 241 ++++++++++++++++++++++++ > drivers/clk/renesas/renesas-cpg-mssr.c | 6 + > drivers/clk/renesas/renesas-cpg-mssr.h | 1 + > 5 files changed, 254 insertions(+) > create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c > > diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig > index 69396e19795903e8..d252150402e86366 100644 > --- a/drivers/clk/renesas/Kconfig > +++ b/drivers/clk/renesas/Kconfig > @@ -33,6 +33,7 @@ config CLK_RENESAS > select CLK_R8A779A0 if ARCH_R8A779A0 > select CLK_R8A779F0 if ARCH_R8A779F0 > select CLK_R8A779G0 if ARCH_R8A779G0 > + select CLK_R8A779H0 if ARCH_R8A779H0 > select CLK_R9A06G032 if ARCH_R9A06G032 > select CLK_R9A07G043 if ARCH_R9A07G043 > select CLK_R9A07G044 if ARCH_R9A07G044 > @@ -165,6 +166,10 @@ config CLK_R8A779G0 > bool "R-Car V4H clock support" if COMPILE_TEST > select CLK_RCAR_GEN4_CPG > > +config CLK_R8A779H0 > + bool "R-Car V4M clock support" if COMPILE_TEST > + select CLK_RCAR_GEN4_CPG > + > config CLK_R9A06G032 > bool "RZ/N1D clock support" if COMPILE_TEST > > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile > index 879a07d445f9056a..f7e18679c3b81b97 100644 > --- a/drivers/clk/renesas/Makefile > +++ b/drivers/clk/renesas/Makefile > @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o > obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o > obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o > obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o > +obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o > obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o > obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o > obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o > diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > new file mode 100644 > index 0000000000000000..1259b8544980f07a > --- /dev/null > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -0,0 +1,241 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset > + * > + * Copyright (C) 2023 Renesas Electronics Corp. > + * > + * Based on r8a779g0-cpg-mssr.c > + */ > + > +#include <linux/bitfield.h> > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/kernel.h> > +#include <linux/soc/renesas/rcar-rst.h> > + > +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> > + > +#include "renesas-cpg-mssr.h" > +#include "rcar-gen4-cpg.h" > + > +enum clk_ids { > + /* Core Clock Outputs exported to DT */ > + LAST_DT_CORE_CLK = R8A779H0_CLK_R, > + > + /* External Input Clocks */ > + CLK_EXTAL, > + CLK_EXTALR, > + > + /* Internal Core Clocks */ > + CLK_MAIN, > + CLK_PLL1, > + CLK_PLL2, > + CLK_PLL3, > + CLK_PLL4, > + CLK_PLL5, > + CLK_PLL6, > + CLK_PLL1_DIV2, > + CLK_PLL2_DIV2, > + CLK_PLL3_DIV2, > + CLK_PLL4_DIV2, > + CLK_PLL4_DIV5, > + CLK_PLL5_DIV2, > + CLK_PLL5_DIV4, > + CLK_PLL6_DIV2, > + CLK_S0, > + CLK_S0_VIO, > + CLK_S0_VC, > + CLK_S0_HSC, > + CLK_SASYNCPER, > + CLK_SV_VIP, > + CLK_SV_IR, > + CLK_IMPASRC, > + CLK_IMPBSRC, > + CLK_VIOSRC, > + CLK_VCSRC, > + CLK_SDSRC, > + CLK_RPCSRC, > + CLK_OCO, > + > + /* Module Clocks */ > + MOD_CLK_BASE > +}; > + > +static const struct cpg_core_clk r8a779h0_core_clks[] = { > + /* External Clock Inputs */ > + DEF_INPUT("extal", CLK_EXTAL), > + DEF_INPUT("extalr", CLK_EXTALR), > + > + /* Internal Core Clocks */ > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), > + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), > + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), > + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), > + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), > + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), > + > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), > + DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), > + DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), > + DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1), > + DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1), > + DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1), > + DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1), > + DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1), > + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), > + DEF_RATE(".oco", CLK_OCO, 32768), > + > + /* Core Clock Outputs */ > + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), > + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), > + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), > + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), > + DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), > + DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), > + DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), > + DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1), > + DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1), > + DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1), > + DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1), > + DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1), > + DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1), > + DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1), > + DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1), > + DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1), > + DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1), > + DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1), > + DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1), > + DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1), > + DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1), > + DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1), > + DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1), > + DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1), > + DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1), > + DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1), > + DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1), > + DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1), > + DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1), > + DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1), > + DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1), > + DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1), > + DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1), > + DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), > + DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1), > + DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1), > + DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1), > + DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1), > + DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1), > + DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1), > + DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1), > + DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1), > + DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1), > + DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1), > + DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1), > + DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1), > + DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1), > + DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1), > + DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1), > + DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1), > + DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1), > + DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), > + DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880), > + DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), > + DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), > + DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), > + > + DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870), > + DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870), > + > + DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC), > + > + DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8), > + DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), > +}; > + > +static const struct mssr_mod_clk r8a779h0_mod_clks[] = { > + DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > + DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > + DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > + DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1), > +}; > + > +/* > + * CPG Clock Data > + */ > +/* > + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC > + * 14 13 (MHz) > + * ------------------------------------------------------------------------ > + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16 > + * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19 > + * 1 0 Prohibited setting > + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32 > + */ > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ > + (((md) & BIT(13)) >> 13)) > + > +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { > + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ > + { 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, }, > + { 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, }, > + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, > + { 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, }, > +}; > + > +static int __init r8a779h0_cpg_mssr_init(struct device *dev) > +{ > + const struct rcar_gen4_cpg_pll_config *cpg_pll_config; > + u32 cpg_mode; > + int error; > + > + error = rcar_rst_read_mode_pins(&cpg_mode); > + if (error) > + return error; > + > + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; > + if (!cpg_pll_config->extal_div) { > + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); > + return -EINVAL; > + } > + > + return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); > +} > + > +const struct cpg_mssr_info r8a779h0_cpg_mssr_info __initconst = { > + /* Core Clocks */ > + .core_clks = r8a779h0_core_clks, > + .num_core_clks = ARRAY_SIZE(r8a779h0_core_clks), > + .last_dt_core_clk = LAST_DT_CORE_CLK, > + .num_total_core_clks = MOD_CLK_BASE, > + > + /* Module Clocks */ > + .mod_clks = r8a779h0_mod_clks, > + .num_mod_clks = ARRAY_SIZE(r8a779h0_mod_clks), > + .num_hw_mod_clks = 30 * 32, > + > + /* Callbacks */ > + .init = r8a779h0_cpg_mssr_init, > + .cpg_clk_register = rcar_gen4_cpg_clk_register, > + > + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, > +}; > diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c > index 23e5a2b46ac132c6..1b421b8097965b70 100644 > --- a/drivers/clk/renesas/renesas-cpg-mssr.c > +++ b/drivers/clk/renesas/renesas-cpg-mssr.c > @@ -871,6 +871,12 @@ static const struct of_device_id cpg_mssr_match[] = { > .compatible = "renesas,r8a779g0-cpg-mssr", > .data = &r8a779g0_cpg_mssr_info, > }, > +#endif > +#ifdef CONFIG_CLK_R8A779H0 > + { > + .compatible = "renesas,r8a779h0-cpg-mssr", > + .data = &r8a779h0_cpg_mssr_info, > + }, > #endif > { /* sentinel */ } > }; > diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h > index 80c5b462924ac343..a1d6e0cbcff94813 100644 > --- a/drivers/clk/renesas/renesas-cpg-mssr.h > +++ b/drivers/clk/renesas/renesas-cpg-mssr.h > @@ -180,6 +180,7 @@ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; > extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info; > extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info; > extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info; > +extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info; > > void __init cpg_mssr_early_init(struct device_node *np, > const struct cpg_mssr_info *info); > -- > 2.34.1 > >
Hi Geert, Thanks for your work. On 2024-01-25 16:34:37 +0100, Geert Uytterhoeven wrote: > From: Duy Nguyen <duy.nguyen.rh@renesas.com> > > Add support for R-Car V4M (R8A779H0) SoC power areas to the R-Car SYSC > driver. > > Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2: > - Add vendor-prefix to DT binding definition header file. > > Changes compared to the BSP: > - Move from drivers/soc/renesas/ to drivers/pmdomain/renesas/, > - Include rcar-gen4-sysc glue from "soc: renesas: rcar-gen4-sysc: > Introduce R-Car Gen4 SYSC driver", > - Remove unneeded includes, > - Align second column, > - Fix names of "a33dga" and "a23dgb" domains, > - Add missing "a3cr[012]" domains. > --- > drivers/pmdomain/renesas/Kconfig | 4 ++ > drivers/pmdomain/renesas/Makefile | 1 + > drivers/pmdomain/renesas/r8a779h0-sysc.c | 55 +++++++++++++++++++++++ > drivers/pmdomain/renesas/rcar-gen4-sysc.c | 3 ++ > drivers/pmdomain/renesas/rcar-gen4-sysc.h | 1 + > 5 files changed, 64 insertions(+) > create mode 100644 drivers/pmdomain/renesas/r8a779h0-sysc.c > > diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kconfig > index 80bf2cf8b60e6f63..54acb4b1ec7c4892 100644 > --- a/drivers/pmdomain/renesas/Kconfig > +++ b/drivers/pmdomain/renesas/Kconfig > @@ -71,6 +71,10 @@ config SYSC_R8A779G0 > bool "System Controller support for R-Car V4H" if COMPILE_TEST > select SYSC_RCAR_GEN4 > > +config SYSC_R8A779H0 > + bool "System Controller support for R-Car V4M" if COMPILE_TEST > + select SYSC_RCAR_GEN4 > + > config SYSC_RMOBILE > bool "System Controller support for R-Mobile" if COMPILE_TEST > > diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/Makefile > index e306e396fc8c10e3..89180f19c23be732 100644 > --- a/drivers/pmdomain/renesas/Makefile > +++ b/drivers/pmdomain/renesas/Makefile > @@ -24,6 +24,7 @@ obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o > obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o > obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o > obj-$(CONFIG_SYSC_R8A779G0) += r8a779g0-sysc.o > +obj-$(CONFIG_SYSC_R8A779H0) += r8a779h0-sysc.o > # Family > obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o > obj-$(CONFIG_SYSC_RCAR_GEN4) += rcar-gen4-sysc.o > diff --git a/drivers/pmdomain/renesas/r8a779h0-sysc.c b/drivers/pmdomain/renesas/r8a779h0-sysc.c > new file mode 100644 > index 0000000000000000..ce2a82183ba8c9ab > --- /dev/null > +++ b/drivers/pmdomain/renesas/r8a779h0-sysc.c > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Renesas R-Car V4M System Controller > + * > + * Copyright (C) 2016-2017 Glider bvba Is 2016-2017 correct? With or without that fixed, Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > + * Copyright (C) 2023 Renesas Electronics Corp > + */ > + > +#include <linux/kernel.h> > + > +#include <dt-bindings/power/renesas,r8a779h0-sysc.h> > + > +#include "rcar-gen4-sysc.h" > + > +static struct rcar_gen4_sysc_area r8a779h0_areas[] __initdata = { > + { "always-on", R8A779H0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, > + { "c4", R8A779H0_PD_C4, R8A779H0_PD_ALWAYS_ON }, > + { "a2e0d0", R8A779H0_PD_A2E0D0, R8A779H0_PD_C4, PD_SCU }, > + { "a1e0d0c0", R8A779H0_PD_A1E0D0C0, R8A779H0_PD_A2E0D0, PD_CPU_NOCR }, > + { "a1e0d0c1", R8A779H0_PD_A1E0D0C1, R8A779H0_PD_A2E0D0, PD_CPU_NOCR }, > + { "a1e0d0c2", R8A779H0_PD_A1E0D0C2, R8A779H0_PD_A2E0D0, PD_CPU_NOCR }, > + { "a1e0d0c3", R8A779H0_PD_A1E0D0C3, R8A779H0_PD_A2E0D0, PD_CPU_NOCR }, > + { "a3cr0", R8A779H0_PD_A3CR0, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR }, > + { "a3cr1", R8A779H0_PD_A3CR1, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR }, > + { "a3cr2", R8A779H0_PD_A3CR2, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR }, > + { "a33dga", R8A779H0_PD_A33DGA, R8A779H0_PD_C4 }, > + { "a23dgb", R8A779H0_PD_A23DGB, R8A779H0_PD_A33DGA }, > + { "a3vip0", R8A779H0_PD_A3VIP0, R8A779H0_PD_C4 }, > + { "a3vip2", R8A779H0_PD_A3VIP2, R8A779H0_PD_C4 }, > + { "a3dul", R8A779H0_PD_A3DUL, R8A779H0_PD_C4 }, > + { "a3isp0", R8A779H0_PD_A3ISP0, R8A779H0_PD_C4 }, > + { "a2cn0", R8A779H0_PD_A2CN0, R8A779H0_PD_C4 }, > + { "a1cn0", R8A779H0_PD_A1CN0, R8A779H0_PD_A2CN0 }, > + { "a1dsp0", R8A779H0_PD_A1DSP0, R8A779H0_PD_A2CN0 }, > + { "a1dsp1", R8A779H0_PD_A1DSP1, R8A779H0_PD_A2CN0 }, > + { "a2imp01", R8A779H0_PD_A2IMP01, R8A779H0_PD_C4 }, > + { "a2psc", R8A779H0_PD_A2PSC, R8A779H0_PD_C4 }, > + { "a2dma", R8A779H0_PD_A2DMA, R8A779H0_PD_C4 }, > + { "a2cv0", R8A779H0_PD_A2CV0, R8A779H0_PD_C4 }, > + { "a2cv1", R8A779H0_PD_A2CV1, R8A779H0_PD_C4 }, > + { "a2cv2", R8A779H0_PD_A2CV2, R8A779H0_PD_C4 }, > + { "a2cv3", R8A779H0_PD_A2CV3, R8A779H0_PD_C4 }, > + { "a3imr0", R8A779H0_PD_A3IMR0, R8A779H0_PD_C4 }, > + { "a3imr1", R8A779H0_PD_A3IMR1, R8A779H0_PD_C4 }, > + { "a3imr2", R8A779H0_PD_A3IMR2, R8A779H0_PD_C4 }, > + { "a3imr3", R8A779H0_PD_A3IMR3, R8A779H0_PD_C4 }, > + { "a3vc", R8A779H0_PD_A3VC, R8A779H0_PD_C4 }, > + { "a3pci", R8A779H0_PD_A3PCI, R8A779H0_PD_C4 }, > + { "a2pciphy", R8A779H0_PD_A2PCIPHY, R8A779H0_PD_A3PCI }, > +}; > + > +const struct rcar_gen4_sysc_info r8a779h0_sysc_info __initconst = { > + .areas = r8a779h0_areas, > + .num_areas = ARRAY_SIZE(r8a779h0_areas), > +}; > diff --git a/drivers/pmdomain/renesas/rcar-gen4-sysc.c b/drivers/pmdomain/renesas/rcar-gen4-sysc.c > index 9e5e6e077abc081c..728248659a97e8cc 100644 > --- a/drivers/pmdomain/renesas/rcar-gen4-sysc.c > +++ b/drivers/pmdomain/renesas/rcar-gen4-sysc.c > @@ -284,6 +284,9 @@ static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = { > #endif > #ifdef CONFIG_SYSC_R8A779G0 > { .compatible = "renesas,r8a779g0-sysc", .data = &r8a779g0_sysc_info }, > +#endif > +#ifdef CONFIG_SYSC_R8A779H0 > + { .compatible = "renesas,r8a779h0-sysc", .data = &r8a779h0_sysc_info }, > #endif > { /* sentinel */ } > }; > diff --git a/drivers/pmdomain/renesas/rcar-gen4-sysc.h b/drivers/pmdomain/renesas/rcar-gen4-sysc.h > index 388cfa8f8f9fd656..fdf843aa51134f87 100644 > --- a/drivers/pmdomain/renesas/rcar-gen4-sysc.h > +++ b/drivers/pmdomain/renesas/rcar-gen4-sysc.h > @@ -40,5 +40,6 @@ struct rcar_gen4_sysc_info { > extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info; > extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info; > extern const struct rcar_gen4_sysc_info r8a779g0_sysc_info; > +extern const struct rcar_gen4_sysc_info r8a779h0_sysc_info; > > #endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */ > -- > 2.34.1 > >
Hi Geert, Thanks for your work. On 2024-01-25 16:34:41 +0100, Geert Uytterhoeven wrote: > From: Hai Pham <hai.pham.ud@renesas.com> > > Add initial support for the Renesas R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - Add vendor-prefixes to DT binding definition header files. > > Changes compared to the BSP: > - Add "-clk" suffix to clock node names, > - Rename "pmu_a76" node to "pmu-a76", > - Drop bogus CPU masks from GICv3 PPI interrupt specifiers, > - Drop hscif0 dmas and dma-names placeholder, > - Add missing hypervisor virtual timer IRQ to timer node. > --- > arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 121 ++++++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0.dtsi > > diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi > new file mode 100644 > index 0000000000000000..a082e2d06b696019 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi > @@ -0,0 +1,121 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the R-Car V4M (R8A779H0) SoC > + * > + * Copyright (C) 2023 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/power/renesas,r8a779h0-sysc.h> > + > +/ { > + compatible = "renesas,r8a779h0"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + a76_0: cpu@0 { > + compatible = "arm,cortex-a76"; > + reg = <0>; > + device_type = "cpu"; > + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; > + }; > + }; > + > + extal_clk: extal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + extalr_clk: extalr-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + pmu-a76 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + /* External SCIF clock - to be overridden by boards that provide it */ > + scif_clk: scif-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + cpg: clock-controller@e6150000 { > + compatible = "renesas,r8a779h0-cpg-mssr"; > + reg = <0 0xe6150000 0 0x4000>; > + clocks = <&extal_clk>, <&extalr_clk>; > + clock-names = "extal", "extalr"; > + #clock-cells = <2>; > + #power-domain-cells = <0>; > + #reset-cells = <1>; > + }; > + > + rst: reset-controller@e6160000 { > + compatible = "renesas,r8a779h0-rst"; > + reg = <0 0xe6160000 0 0x4000>; > + }; > + > + sysc: system-controller@e6180000 { > + compatible = "renesas,r8a779h0-sysc"; > + reg = <0 0xe6180000 0 0x4000>; > + #power-domain-cells = <1>; > + }; > + > + hscif0: serial@e6540000 { > + compatible = "renesas,hscif-r8a779h0", > + "renesas,rcar-gen4-hscif", "renesas,hscif"; > + reg = <0 0xe6540000 0 0x60>; > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 514>, > + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; > + resets = <&cpg 514>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@f1000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0xf1000000 0 0x20000>, > + <0x0 0xf1060000 0 0x110000>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + prr: chipid@fff00044 { > + compatible = "renesas,prr"; > + reg = <0 0xfff00044 0 4>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; > + }; > +}; > -- > 2.34.1 > >
Hi Geert, On 2024-01-25 16:34:42 +0100, Geert Uytterhoeven wrote: > Add initial support for the Renesas Gray Hawk Single board, which is > based on the R-Car V4M (R8A779H0) SoC: > - Memory, > - Crystal oscillators, > - Serial console. > > Based on the White Hawk Single DTS, and on a patch for the Gray Hawk > board stack in the BSP by Hai Pham. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - Add SoC name to top-level comment. > --- > arch/arm64/boot/dts/renesas/Makefile | 2 + > .../dts/renesas/r8a779h0-gray-hawk-single.dts | 52 +++++++++++++++++++ > 2 files changed, 54 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts > > diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile > index 1d7d69657a1f0559..4c5ac5f02829ff58 100644 > --- a/arch/arm64/boot/dts/renesas/Makefile > +++ b/arch/arm64/boot/dts/renesas/Makefile > @@ -86,6 +86,8 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo > r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo > dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb > > +dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb > + > dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb > r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo > dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb > diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts > new file mode 100644 > index 0000000000000000..1ed404712d823871 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts > @@ -0,0 +1,52 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the R-Car V4M Gray Hawk Single board > + * > + * Copyright (C) 2023 Renesas Electronics Corp. > + * Copyright (C) 2024 Glider bv > + */ > + > +/dts-v1/; > +#include "r8a779h0.dtsi" > + > +/ { > + model = "Renesas Gray Hawk Single board based on r8a779h0"; > + compatible = "renesas,gray-hawk-single", "renesas,r8a779h0"; > + > + aliases { > + serial0 = &hscif0; > + }; > + > + chosen { > + bootargs = "ignore_loglevel"; > + stdout-path = "serial0:921600n8"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x78000000>; > + }; > + > + memory@480000000 { > + device_type = "memory"; > + reg = <0x4 0x80000000 0x1 0x80000000>; > + }; > +}; > + > +&extal_clk { > + clock-frequency = <16666666>; > +}; > + > +&extalr_clk { > + clock-frequency = <32768>; > +}; > + > +&hscif0 { > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&scif_clk { > + clock-frequency = <24000000>; > +}; > -- > 2.34.1 > >
Hi Niklas, On Thu, Jan 25, 2024 at 7:46 PM Niklas Söderlund <niklas.soderlund@ragnatech.se> wrote: > On 2024-01-25 16:34:37 +0100, Geert Uytterhoeven wrote: > > From: Duy Nguyen <duy.nguyen.rh@renesas.com> > > > > Add support for R-Car V4M (R8A779H0) SoC power areas to the R-Car SYSC > > driver. > > > > Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > v2: > > - Add vendor-prefix to DT binding definition header file. > > --- /dev/null > > +++ b/drivers/pmdomain/renesas/r8a779h0-sysc.c > > @@ -0,0 +1,55 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Renesas R-Car V4M System Controller > > + * > > + * Copyright (C) 2016-2017 Glider bvba > > Is 2016-2017 correct? With or without that fixed, That must have been copied from r8a7795-sysc.c... As the layout of R-Car V4M is completely different from R-Car H3, I will drop that line (with or without reposting). > Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks! Gr{oetje,eeting}s, Geert
On Thu, 25 Jan 2024 at 16:34, Geert Uytterhoeven <geert+renesas@glider.be> wrote: > > Hi all, > > This patch series adds initial support for the Renesas R-Car V4M > (R8A779G0) SoC and the Renesas Gray Hawk Single development board. > > As both driver code and DTS have hard dependencies on DT binding > definitions, most patches in this series are supposed to go in through > the renesas-devel and/or renesas-clk trees, using a shared branch for DT > binding definitions, as usual. For the PM domain patches (03, 04, 09), > Ulf already offered to apply these to his pmdomain tree, and provide an > immutable "dt" branch, to be pulled in my renesas-devel tree. Patch 3,4 and 9 (I dropped the copyright line in patch9, as pointed out by Niklas) applied for next, thanks! Patch 3,4 are also available at the immutable dt branch for you to pull in. Kind regards Uffe > > Changes compared to v1[1]: > - Add Acked-by, Reviewed-by, > - Add vendor-prefix to DT binding definition header file names and > update include guards, > - Add "board" to compatible comment, > - Add missing CP core clock, > - Add SoC name to top-level comment. > > For testing, this series can be found at > https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/v4m-gray-hawk-single-v2 > > Thanks for your comments! > > [1] "[PATCH 00/15] arm64: renesas: Add R-Car V4M and Gray Hawk Single > support" > https://lore.kernel.org/linux-renesas-soc/cover.1704726960.git.geert+renesas@glider.be > > Cong Dang (1): > clk: renesas: cpg-mssr: Add support for R-Car V4M > > Duy Nguyen (6): > dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions > dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support > dt-bindings: power: Add r8a779h0 SYSC power domain definitions > pmdomain: renesas: r8a779h0-sysc: Add r8a779h0 support > soc: renesas: Identify R-Car V4M > soc: renesas: rcar-rst: Add support for R-Car V4M > > Geert Uytterhoeven (6): > dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support > dt-bindings: reset: renesas,rst: Document R-Car V4M support > dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single > clk: renesas: rcar-gen4: Add support for FRQCRC1 > soc: renesas: Introduce ARCH_RCAR_GEN4 > arm64: dts: renesas: Add Gray Hawk Single board support > > Hai Pham (1): > arm64: dts: renesas: Add Renesas R8A779H0 SoC support > > Linh Phung (1): > arm64: defconfig: Enable R8A779H0 SoC > > .../bindings/clock/renesas,cpg-mssr.yaml | 1 + > .../bindings/power/renesas,rcar-sysc.yaml | 1 + > .../bindings/reset/renesas,rst.yaml | 1 + > .../bindings/soc/renesas/renesas.yaml | 6 + > arch/arm64/boot/dts/renesas/Makefile | 2 + > .../dts/renesas/r8a779h0-gray-hawk-single.dts | 52 ++++ > arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 121 +++++++++ > arch/arm64/configs/defconfig | 1 + > drivers/clk/renesas/Kconfig | 5 + > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r8a779h0-cpg-mssr.c | 241 ++++++++++++++++++ > drivers/clk/renesas/rcar-gen4-cpg.c | 10 +- > drivers/clk/renesas/renesas-cpg-mssr.c | 6 + > drivers/clk/renesas/renesas-cpg-mssr.h | 1 + > drivers/pmdomain/renesas/Kconfig | 4 + > drivers/pmdomain/renesas/Makefile | 1 + > drivers/pmdomain/renesas/r8a779h0-sysc.c | 55 ++++ > drivers/pmdomain/renesas/rcar-gen4-sysc.c | 3 + > drivers/pmdomain/renesas/rcar-gen4-sysc.h | 1 + > drivers/soc/renesas/Kconfig | 17 +- > drivers/soc/renesas/rcar-rst.c | 1 + > drivers/soc/renesas/renesas-soc.c | 8 + > .../clock/renesas,r8a779h0-cpg-mssr.h | 96 +++++++ > .../dt-bindings/power/renesas,r8a779h0-sysc.h | 49 ++++ > 24 files changed, 679 insertions(+), 5 deletions(-) > create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts > create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0.dtsi > create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c > create mode 100644 drivers/pmdomain/renesas/r8a779h0-sysc.c > create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h > create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h > > -- > 2.34.1 > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Ulf, On Tue, Jan 30, 2024 at 2:11 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > On Thu, 25 Jan 2024 at 16:34, Geert Uytterhoeven > <geert+renesas@glider.be> wrote: > > This patch series adds initial support for the Renesas R-Car V4M > > (R8A779G0) SoC and the Renesas Gray Hawk Single development board. > > > > As both driver code and DTS have hard dependencies on DT binding > > definitions, most patches in this series are supposed to go in through > > the renesas-devel and/or renesas-clk trees, using a shared branch for DT > > binding definitions, as usual. For the PM domain patches (03, 04, 09), > > Ulf already offered to apply these to his pmdomain tree, and provide an > > immutable "dt" branch, to be pulled in my renesas-devel tree. > > Patch 3,4 and 9 (I dropped the copyright line in patch9, as pointed > out by Niklas) applied for next, thanks! > > Patch 3,4 are also available at the immutable dt branch for you to pull in. Thank you! I have pulled the immutable branch, added the remaining DT binding definitions, and queued all remaining patches. Gr{oetje,eeting}s, Geert
Hi Ulf, On Wed, Jan 31, 2024 at 3:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Tue, Jan 30, 2024 at 2:11 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > On Thu, 25 Jan 2024 at 16:34, Geert Uytterhoeven > > <geert+renesas@glider.be> wrote: > > > This patch series adds initial support for the Renesas R-Car V4M > > > (R8A779G0) SoC and the Renesas Gray Hawk Single development board. > > > > > > As both driver code and DTS have hard dependencies on DT binding > > > definitions, most patches in this series are supposed to go in through > > > the renesas-devel and/or renesas-clk trees, using a shared branch for DT > > > binding definitions, as usual. For the PM domain patches (03, 04, 09), > > > Ulf already offered to apply these to his pmdomain tree, and provide an > > > immutable "dt" branch, to be pulled in my renesas-devel tree. > > > > Patch 3,4 and 9 (I dropped the copyright line in patch9, as pointed > > out by Niklas) applied for next, thanks! > > > > Patch 3,4 are also available at the immutable dt branch for you to pull in. > > Thank you! > > I have pulled the immutable branch, added the remaining DT binding > definitions, and queued all remaining patches. It looks like you have applied copies of all commits on the "dt" branch to the "next" branch, so now there are two copies? See the output of "git range-diff v6.8-rc1..pmdomain/dt v6.8-rc4..pmdomain/next". Gr{oetje,eeting}s, Geert
On Wed, 14 Feb 2024 at 09:35, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Ulf, > > On Wed, Jan 31, 2024 at 3:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Jan 30, 2024 at 2:11 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > > On Thu, 25 Jan 2024 at 16:34, Geert Uytterhoeven > > > <geert+renesas@glider.be> wrote: > > > > This patch series adds initial support for the Renesas R-Car V4M > > > > (R8A779G0) SoC and the Renesas Gray Hawk Single development board. > > > > > > > > As both driver code and DTS have hard dependencies on DT binding > > > > definitions, most patches in this series are supposed to go in through > > > > the renesas-devel and/or renesas-clk trees, using a shared branch for DT > > > > binding definitions, as usual. For the PM domain patches (03, 04, 09), > > > > Ulf already offered to apply these to his pmdomain tree, and provide an > > > > immutable "dt" branch, to be pulled in my renesas-devel tree. > > > > > > Patch 3,4 and 9 (I dropped the copyright line in patch9, as pointed > > > out by Niklas) applied for next, thanks! > > > > > > Patch 3,4 are also available at the immutable dt branch for you to pull in. > > > > Thank you! > > > > I have pulled the immutable branch, added the remaining DT binding > > definitions, and queued all remaining patches. > > It looks like you have applied copies of all commits on the "dt" > branch to the "next" > branch, so now there are two copies? > > See the output of "git range-diff v6.8-rc1..pmdomain/dt > v6.8-rc4..pmdomain/next". I screwed up - and thanks for pointing this out! Problem is taken care of now. Kind regards Uffe
Hi all, This patch series adds initial support for the Renesas R-Car V4M (R8A779G0) SoC and the Renesas Gray Hawk Single development board. As both driver code and DTS have hard dependencies on DT binding definitions, most patches in this series are supposed to go in through the renesas-devel and/or renesas-clk trees, using a shared branch for DT binding definitions, as usual. For the PM domain patches (03, 04, 09), Ulf already offered to apply these to his pmdomain tree, and provide an immutable "dt" branch, to be pulled in my renesas-devel tree. Changes compared to v1[1]: - Add Acked-by, Reviewed-by, - Add vendor-prefix to DT binding definition header file names and update include guards, - Add "board" to compatible comment, - Add missing CP core clock, - Add SoC name to top-level comment. For testing, this series can be found at https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/v4m-gray-hawk-single-v2 Thanks for your comments! [1] "[PATCH 00/15] arm64: renesas: Add R-Car V4M and Gray Hawk Single support" https://lore.kernel.org/linux-renesas-soc/cover.1704726960.git.geert+renesas@glider.be Cong Dang (1): clk: renesas: cpg-mssr: Add support for R-Car V4M Duy Nguyen (6): dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support dt-bindings: power: Add r8a779h0 SYSC power domain definitions pmdomain: renesas: r8a779h0-sysc: Add r8a779h0 support soc: renesas: Identify R-Car V4M soc: renesas: rcar-rst: Add support for R-Car V4M Geert Uytterhoeven (6): dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support dt-bindings: reset: renesas,rst: Document R-Car V4M support dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single clk: renesas: rcar-gen4: Add support for FRQCRC1 soc: renesas: Introduce ARCH_RCAR_GEN4 arm64: dts: renesas: Add Gray Hawk Single board support Hai Pham (1): arm64: dts: renesas: Add Renesas R8A779H0 SoC support Linh Phung (1): arm64: defconfig: Enable R8A779H0 SoC .../bindings/clock/renesas,cpg-mssr.yaml | 1 + .../bindings/power/renesas,rcar-sysc.yaml | 1 + .../bindings/reset/renesas,rst.yaml | 1 + .../bindings/soc/renesas/renesas.yaml | 6 + arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r8a779h0-gray-hawk-single.dts | 52 ++++ arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 121 +++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a779h0-cpg-mssr.c | 241 ++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.c | 10 +- drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + drivers/pmdomain/renesas/Kconfig | 4 + drivers/pmdomain/renesas/Makefile | 1 + drivers/pmdomain/renesas/r8a779h0-sysc.c | 55 ++++ drivers/pmdomain/renesas/rcar-gen4-sysc.c | 3 + drivers/pmdomain/renesas/rcar-gen4-sysc.h | 1 + drivers/soc/renesas/Kconfig | 17 +- drivers/soc/renesas/rcar-rst.c | 1 + drivers/soc/renesas/renesas-soc.c | 8 + .../clock/renesas,r8a779h0-cpg-mssr.h | 96 +++++++ .../dt-bindings/power/renesas,r8a779h0-sysc.h | 49 ++++ 24 files changed, 679 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0.dtsi create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c create mode 100644 drivers/pmdomain/renesas/r8a779h0-sysc.c create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h