| Message ID | 20240105092344.23778-1-wangfeng@eswincomputing.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Fix avl-type operand index error for ZVBC | expand |
LGTM.
juzhe.zhong@rivai.ai
From: Feng Wang
Date: 2024-01-05 17:23
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Fix avl-type operand index error for ZVBC
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type index of zvbc ins is error,it should be operand[8]
not operand[5].
gcc/ChangeLog:
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
gcc/config/riscv/vector.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3d2c1c3ce8f..e99a312b5b6 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -864,9 +864,9 @@
vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
- vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll")
+ vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll")
(const_int 8)
- (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh")
+ (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
(const_int 5)
(eq_attr "type" "vimuladd,vfmuladd")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3d2c1c3ce8f..e99a312b5b6 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -864,9 +864,9 @@ vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ - vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll") + vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") (const_int 8) - (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh") + (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") (const_int 5) (eq_attr "type" "vimuladd,vfmuladd")