Message ID | 20231208071200.3238127-1-hongtao.liu@intel.com |
---|---|
State | New |
Headers | show |
Series | [ICE] Support vpcmov for V4HF/V4BF/V2HF/V2BF under TARGET_XOP. | expand |
On Fri, Dec 08, 2023 at 03:12:00PM +0800, liuhongt wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ready push to trunk. > > gcc/ChangeLog: > > PR target/112904 > * config/i386/mmx.md (*xop_pcmov_<mode>): New define_insn. > > gcc/testsuite/ChangeLog: > > * g++.target/i386/pr112904.C: New test. The new test FAILs on i686-linux and even on x86_64-linux I think it doesn't actually test what was reported, unless one performs testing with -march= for some XOP enabled CPU or -mxop. The following patch fixes that, tested on x86_64-linux with make check-g++ RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mno-sse/-mno-mmx,-m64\} i386.exp=pr112904.C' Ok for trunk? 2023-12-13 Jakub Jelinek <jakub@redhat.com> * g++.target/i386/pr112904.C: Add dg-do compile, dg-options -mxop and for ia32 also dg-additional-options -mmmx. --- gcc/testsuite/g++.target/i386/pr112904.C.jj 2023-12-11 08:31:59.001938798 +0100 +++ gcc/testsuite/g++.target/i386/pr112904.C 2023-12-13 12:54:50.318521637 +0100 @@ -1,3 +1,8 @@ +// PR target/112904 +// { dg-do compile } +// { dg-options "-mxop" } +// { dg-additional-options "-mmmx" { target ia32 } } + typedef _Float16 v4hf __attribute__((vector_size(8))); typedef short v4hi __attribute__((vector_size(8))); typedef _Float16 v2hf __attribute__((vector_size(4))); Jakub
On Wed, Dec 13, 2023 at 7:59 PM Jakub Jelinek <jakub@redhat.com> wrote: > > On Fri, Dec 08, 2023 at 03:12:00PM +0800, liuhongt wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > > Ready push to trunk. > > > > gcc/ChangeLog: > > > > PR target/112904 > > * config/i386/mmx.md (*xop_pcmov_<mode>): New define_insn. > > > > gcc/testsuite/ChangeLog: > > > > * g++.target/i386/pr112904.C: New test. > > The new test FAILs on i686-linux and even on x86_64-linux I think > it doesn't actually test what was reported, unless one performs testing > with -march= for some XOP enabled CPU or -mxop. > > The following patch fixes that, tested on x86_64-linux with > make check-g++ RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mno-sse/-mno-mmx,-m64\} i386.exp=pr112904.C' > Ok for trunk? Ok. Sorry for the inconvenience, I must have missed something in my tester. > > 2023-12-13 Jakub Jelinek <jakub@redhat.com> > > * g++.target/i386/pr112904.C: Add dg-do compile, dg-options -mxop > and for ia32 also dg-additional-options -mmmx. > > --- gcc/testsuite/g++.target/i386/pr112904.C.jj 2023-12-11 08:31:59.001938798 +0100 > +++ gcc/testsuite/g++.target/i386/pr112904.C 2023-12-13 12:54:50.318521637 +0100 > @@ -1,3 +1,8 @@ > +// PR target/112904 > +// { dg-do compile } > +// { dg-options "-mxop" } > +// { dg-additional-options "-mmmx" { target ia32 } } > + > typedef _Float16 v4hf __attribute__((vector_size(8))); > typedef short v4hi __attribute__((vector_size(8))); > typedef _Float16 v2hf __attribute__((vector_size(4))); > > > Jakub >
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a07a921b739..06d6c57876b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -4136,6 +4136,17 @@ (define_insn "*xop_pcmov_<mode>" [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) +(define_insn "*xop_pcmov_<mode>" + [(set (match_operand:V4F_64 0 "register_operand" "=x") + (if_then_else:V4F_64 + (match_operand:V4F_64 3 "register_operand" "x") + (match_operand:V4F_64 1 "register_operand" "x") + (match_operand:V4F_64 2 "register_operand" "x")))] + "TARGET_XOP && TARGET_MMX_WITH_SSE" + "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse4arg") + (set_attr "mode" "TI")]) + (define_insn "*xop_pcmov_<mode>" [(set (match_operand:VI_16_32 0 "register_operand" "=x") (if_then_else:VI_16_32 @@ -4147,6 +4158,17 @@ (define_insn "*xop_pcmov_<mode>" [(set_attr "type" "sse4arg") (set_attr "mode" "TI")]) +(define_insn "*xop_pcmov_<mode>" + [(set (match_operand:V2F_32 0 "register_operand" "=x") + (if_then_else:V2F_32 + (match_operand:V2F_32 3 "register_operand" "x") + (match_operand:V2F_32 1 "register_operand" "x") + (match_operand:V2F_32 2 "register_operand" "x")))] + "TARGET_XOP" + "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse4arg") + (set_attr "mode" "TI")]) + ;; XOP permute instructions (define_insn "mmx_ppermv64" [(set (match_operand:V8QI 0 "register_operand" "=x") diff --git a/gcc/testsuite/g++.target/i386/pr112904.C b/gcc/testsuite/g++.target/i386/pr112904.C new file mode 100644 index 00000000000..556be921197 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr112904.C @@ -0,0 +1,27 @@ +typedef _Float16 v4hf __attribute__((vector_size(8))); +typedef short v4hi __attribute__((vector_size(8))); +typedef _Float16 v2hf __attribute__((vector_size(4))); +typedef short v2hi __attribute__((vector_size(4))); + +typedef __bf16 v4bf __attribute__((vector_size(8))); +typedef __bf16 v2bf __attribute__((vector_size(4))); + +v4hf foo(v4hf a, v4hf b, v4hi c) +{ + return c ? a : b; +} + +v2hf foo1(v2hf a, v2hf b, v2hi c) +{ + return c ? a : b; +} + +v4bf foo(v4bf a, v4bf b, v4hi c) +{ + return c ? a : b; +} + +v2bf foo1(v2bf a, v2bf b, v2hi c) +{ + return c ? a : b; +}