| Message ID | 20231213091250.30539-1-wangfeng@eswincomputing.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/4] RISC-V:Add crypto vector implied ISA info. | expand |
LGTM On Wed, Dec 13, 2023 at 5:14 PM Feng Wang <wangfeng@eswincomputing.com> wrote: > > Patch v2: Change the implied ISA info using the minimum set and add > dependencies info into the python script. > > Due to the crypto vector entension is depend on the Vector extension, > so the "v" info is added into implied ISA info with the corresponding > crypto vector extension. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Modify implied ISA info. > * config/riscv/arch-canonicalize: Add crypto vector implied info. > --- > gcc/common/config/riscv/riscv-common.cc | 9 +++++++++ > gcc/config/riscv/arch-canonicalize | 21 +++++++++++++++------ > 2 files changed, 24 insertions(+), 6 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 4d5a2f874a2..76987598143 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -145,6 +145,15 @@ static const riscv_implied_info_t riscv_implied_info[] = > {"zvksc", "zvbc"}, > {"zvksg", "zvks"}, > {"zvksg", "zvkg"}, > + {"zvbb", "zvkb"}, > + {"zvbc", "zve64x"}, > + {"zvkb", "zve32x"}, > + {"zvkg", "zve32x"}, > + {"zvkned", "zve32x"}, > + {"zvknha", "zve32x"}, > + {"zvknhb", "zve64x"}, > + {"zvksed", "zve32x"}, > + {"zvksh", "zve32x"}, > > {"zfh", "zfhmin"}, > {"zfhmin", "f"}, > diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize > index ea2f67a0944..a8f47a1752b 100755 > --- a/gcc/config/riscv/arch-canonicalize > +++ b/gcc/config/riscv/arch-canonicalize > @@ -69,12 +69,21 @@ IMPLIED_EXT = { > "zvl32768b" : ["zvl16384b"], > "zvl65536b" : ["zvl32768b"], > > - "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"], > - "zvknc" : ["zvkn", "zvbc"], > - "zvkng" : ["zvkn", "zvkg"], > - "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"], > - "zvksc" : ["zvks", "zvbc"], > - "zvksg" : ["zvks", "zvkg"], > + "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"], > + "zvknc" : ["zvkn", "zvbc"], > + "zvkng" : ["zvkn", "zvkg"], > + "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"], > + "zvksc" : ["zvks", "zvbc"], > + "zvksg" : ["zvks", "zvkg"], > + "zvbb" : ["zvkb"], > + "zvbc" : ["zve64x"], > + "zvkb" : ["zve32x"], > + "zvkg" : ["zve32x"], > + "zvkned" : ["zve32x"], > + "zvknha" : ["zve32x"], > + "zvknhb" : ["zve64x"], > + "zvksed" : ["zve32x"], > + "zvksh" : ["zve32x"], > } > > def arch_canonicalize(arch, isa_spec): > -- > 2.17.1 >
Hi, Kito. Vector crypto ISA is ratifed, but intrinsics is not. I wonder what the schedule of vector crypto intrinsic ? Will it be ratified before GCC-14 release (I personally think intrinsics stuff can be considered to be merged until the end of GCC-14, like I did in GCC-13 push rvv-intrinsic v0.11)? Intrinsics stuff should be very safe. juzhe.zhong@rivai.ai From: Kito Cheng Date: 2023-12-13 18:09 To: Feng Wang CC: gcc-patches; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan Subject: Re: [PATCH v2 1/4] RISC-V:Add crypto vector implied ISA info. LGTM On Wed, Dec 13, 2023 at 5:14 PM Feng Wang <wangfeng@eswincomputing.com> wrote: > > Patch v2: Change the implied ISA info using the minimum set and add > dependencies info into the python script. > > Due to the crypto vector entension is depend on the Vector extension, > so the "v" info is added into implied ISA info with the corresponding > crypto vector extension. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Modify implied ISA info. > * config/riscv/arch-canonicalize: Add crypto vector implied info. > --- > gcc/common/config/riscv/riscv-common.cc | 9 +++++++++ > gcc/config/riscv/arch-canonicalize | 21 +++++++++++++++------ > 2 files changed, 24 insertions(+), 6 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 4d5a2f874a2..76987598143 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -145,6 +145,15 @@ static const riscv_implied_info_t riscv_implied_info[] = > {"zvksc", "zvbc"}, > {"zvksg", "zvks"}, > {"zvksg", "zvkg"}, > + {"zvbb", "zvkb"}, > + {"zvbc", "zve64x"}, > + {"zvkb", "zve32x"}, > + {"zvkg", "zve32x"}, > + {"zvkned", "zve32x"}, > + {"zvknha", "zve32x"}, > + {"zvknhb", "zve64x"}, > + {"zvksed", "zve32x"}, > + {"zvksh", "zve32x"}, > > {"zfh", "zfhmin"}, > {"zfhmin", "f"}, > diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize > index ea2f67a0944..a8f47a1752b 100755 > --- a/gcc/config/riscv/arch-canonicalize > +++ b/gcc/config/riscv/arch-canonicalize > @@ -69,12 +69,21 @@ IMPLIED_EXT = { > "zvl32768b" : ["zvl16384b"], > "zvl65536b" : ["zvl32768b"], > > - "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"], > - "zvknc" : ["zvkn", "zvbc"], > - "zvkng" : ["zvkn", "zvkg"], > - "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"], > - "zvksc" : ["zvks", "zvbc"], > - "zvksg" : ["zvks", "zvkg"], > + "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"], > + "zvknc" : ["zvkn", "zvbc"], > + "zvkng" : ["zvkn", "zvkg"], > + "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"], > + "zvksc" : ["zvks", "zvbc"], > + "zvksg" : ["zvks", "zvkg"], > + "zvbb" : ["zvkb"], > + "zvbc" : ["zve64x"], > + "zvkb" : ["zve32x"], > + "zvkg" : ["zve32x"], > + "zvkned" : ["zve32x"], > + "zvknha" : ["zve32x"], > + "zvknhb" : ["zve64x"], > + "zvksed" : ["zve32x"], > + "zvksh" : ["zve32x"], > } > > def arch_canonicalize(arch, isa_spec): > -- > 2.17.1 >
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4d5a2f874a2..76987598143 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -145,6 +145,15 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvksc", "zvbc"}, {"zvksg", "zvks"}, {"zvksg", "zvkg"}, + {"zvbb", "zvkb"}, + {"zvbc", "zve64x"}, + {"zvkb", "zve32x"}, + {"zvkg", "zve32x"}, + {"zvkned", "zve32x"}, + {"zvknha", "zve32x"}, + {"zvknhb", "zve64x"}, + {"zvksed", "zve32x"}, + {"zvksh", "zve32x"}, {"zfh", "zfhmin"}, {"zfhmin", "f"}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index ea2f67a0944..a8f47a1752b 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -69,12 +69,21 @@ IMPLIED_EXT = { "zvl32768b" : ["zvl16384b"], "zvl65536b" : ["zvl32768b"], - "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"], - "zvknc" : ["zvkn", "zvbc"], - "zvkng" : ["zvkn", "zvkg"], - "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"], - "zvksc" : ["zvks", "zvbc"], - "zvksg" : ["zvks", "zvkg"], + "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"], + "zvknc" : ["zvkn", "zvbc"], + "zvkng" : ["zvkn", "zvkg"], + "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"], + "zvksc" : ["zvks", "zvbc"], + "zvksg" : ["zvks", "zvkg"], + "zvbb" : ["zvkb"], + "zvbc" : ["zve64x"], + "zvkb" : ["zve32x"], + "zvkg" : ["zve32x"], + "zvkned" : ["zve32x"], + "zvknha" : ["zve32x"], + "zvknhb" : ["zve64x"], + "zvksed" : ["zve32x"], + "zvksh" : ["zve32x"], } def arch_canonicalize(arch, isa_spec):