| Message ID | 20231113185607.1756-2-james.quinlan@broadcom.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: brcmstb: Configure appropriate HW CLKREQ# mode | expand |
On Mon, Nov 13, 2023 at 01:56:05PM -0500, Jim Quinlan wrote: > The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- > requires the driver to deliberately place the RC HW one of three CLKREQ# > modes. The "brcm,clkreq-mode" property allows the user to override the > default setting. If this property is omitted, the default mode shall be > "default". > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor
On Mon, 13 Nov 2023 13:56:05 -0500, Jim Quinlan wrote: > The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- > requires the driver to deliberately place the RC HW one of three CLKREQ# > modes. The "brcm,clkreq-mode" property allows the user to override the > default setting. If this property is omitted, the default mode shall be > "default". > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > --- > .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..22491f7f8852 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,24 @@ properties: aspm-no-l0s: true + brcm,clkreq-mode: + description: A string that determines the operating + clkreq mode of the PCIe RC HW with respect to controlling the refclk + signal. There are three different modes -- "safe", which drives the + refclk signal unconditionally and will work for all devices but does + not provide any power savings; "no-l1ss" -- which provides Clock + Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) + power savings. If the downstream device connected to the RC is L1SS + capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, + potentially hanging the system; "default" -- which provides L0s, L1, + and L1SS, but not compliant to provide Clock Power Management; + specifically, may not be able to meet the T_CLRon max timing of 400ns + as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI + Express Mini CEM 2.1 specification. This situation is atypical and + should happen only with older devices. + $ref: /schemas/types.yaml#/definitions/string + enum: [ safe, no-l1ss, default ] + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to
The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver to deliberately place the RC HW one of three CLKREQ# modes. The "brcm,clkreq-mode" property allows the user to override the default setting. If this property is omitted, the default mode shall be "default". Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)