| Message ID | 20231023-display-support-v1-0-5c860ed5c33b@baylibre.com |
|---|---|
| Headers | show |
| Series | Add display support for the MT8365-EVK board | expand |
Il 23/10/23 16:40, amergnat@baylibre.com ha scritto: > From: Fabien Parent <fparent@baylibre.com> > > MT8365 requires an additional clock for DPI. Add support for that > additional clock. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> I'm not convinced that this is right... at all. From a fast check of the MT8365 DPI clocks, I can see that the DPI0 clock declares parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN (which is the GATE clock, enabling output of DPIx VPLL?). But then, there's even more: no clock ever references the CLK_TOP_DPI0_SEL nor the CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other platforms, that is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?! I have many questions now: * Two PLLs are apparently brought up, but which one is the right one?! * Is the LVDS PLL really used for DisplayPort? (dpi0_sel) * Is the VPLL_DPIx PLL used for DisplayPort instead? (dpi0_dpi0) * Why is the LVDSTX_PXL clock using the same PLL as DPI0?! * Why is the VPLL_DPIx gate never enabled? * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel instead? * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock for the DPI1 controller? Is there any DPI1 controller, even?! * Why is there a DPI1 MUX, if there's no DPI1 controller?! Answering all those questions will lead you to the right change, which I believe to be in the clock drivers, not here in mtk_dpi.c. Cheers! Angelo
Il 23/10/23 16:40, amergnat@baylibre.com ha scritto: > From: Fabien Parent <fparent@baylibre.com> > > Add DRM support for MT8365 SoC. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 24/10/2023 11:12, AngeloGioacchino Del Regno wrote: > Il 23/10/23 16:40, amergnat@baylibre.com ha scritto: >> From: Fabien Parent <fparent@baylibre.com> >> >> MT8365 requires an additional clock for DPI. Add support for that >> additional clock. >> >> Signed-off-by: Fabien Parent <fparent@baylibre.com> >> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > > I'm not convinced that this is right... at all. > > From a fast check of the MT8365 DPI clocks, I can see that the DPI0 > clock declares > parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN > (which is the > GATE clock, enabling output of DPIx VPLL?). > > But then, there's even more: no clock ever references the > CLK_TOP_DPI0_SEL nor the > CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other > platforms, that > is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?! AFAI see into mt8365 documentation, there is no TVDPLL, only LVDSPLL > > I have many questions now: > * Two PLLs are apparently brought up, but which one is the right one?! > * Is the LVDS PLL really used for DisplayPort? (dpi0_sel) Seems to be LVDS enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- clk26m 18 19 1 26000000 0 0 Y vpll_dpix 1 1 0 75000000 0 0 50000 Y mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N mm_dpi0_dpi0 1 1 0 75000000 0 0 50000 Y vpll_dpix_en 0 0 0 75000000 0 0 50000 N lvdspll 1 1 0 283999497 0 0 50000 Y lvdspll_d16 0 0 0 17749968 0 0 50000 Y lvdspll_d8 0 0 0 35499937 0 0 50000 Y lvdspll_d4 0 0 0 70999874 0 0 50000 Y lvdspll_d2 1 1 0 141999748 0 0 50000 Y dpi0_sel 1 1 0 141999748 0 0 50000 Y dpi1_sel 0 0 0 141999748 0 0 50000 N mmpll 1 1 0 456999909 0 0 50000 Y mmpll_ck 1 1 0 456999909 0 0 50000 Y mm_sel 15 15 0 456999909 0 0 50000 Y mm_dpi0 1 1 0 456999909 0 0 50000 Y > * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel > instead? I'm agree with you. After few change, it works. - GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20), + GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20), - clocks = <&topckgen CLK_TOP_DPI0_SEL>, + clocks = <&mmsys CLK_MM_DPI0_DPI0>, enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- vpll_dpix 0 0 0 75000000 0 0 50000 Y mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N vpll_dpix_en 0 0 0 75000000 0 0 50000 N lvdspll 1 1 0 283999497 0 0 50000 Y lvdspll_d16 0 0 0 17749968 0 0 50000 Y lvdspll_d8 0 0 0 35499937 0 0 50000 Y lvdspll_d4 0 0 0 70999874 0 0 50000 Y lvdspll_d2 1 1 0 141999748 0 0 50000 Y dpi0_sel 1 1 0 141999748 0 0 50000 Y mm_dpi0_dpi0 1 1 0 141999748 0 0 50000 Y dpi1_sel 0 0 0 141999748 0 0 50000 N mmpll 1 1 0 456999909 0 0 50000 Y mmpll_d2 0 0 0 228499954 0 0 50000 Y mmpll_ck 1 1 0 456999909 0 0 50000 Y mm_sel 15 15 0 456999909 0 0 50000 Y mm_dpi0 1 1 0 456999909 0 0 50000 Y > * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock > for the DPI1 controller? Is there any DPI1 controller, even?! DPI1 isn't documented. > * Why is there a DPI1 MUX, if there's no DPI1 controller?! Good question, I don't know. Legacy of the downstream code. That will be fixed for the next version.
The purpose of this series is to add the display support for the mt8365-evk. This is the list of HWs / IPs support added: - Connectors (HW): - HDMI - MIPI DSI (Mobile Industry Processor Interface Display Serial Interface) - HDMI bridge (it66121) - DSI pannel (startek,kd070fhfid015) - SoC display blocks (IP): - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) The Mediatek DSI, DPI and DRM drivers are also improved. Regards, Alex Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- Alexandre Mergnat (14): dt-bindings: display: mediatek: aal: add binding for MT8365 SoC dt-bindings: display: mediatek: ccorr: add binding for MT8365 SoC dt-bindings: display: mediatek: color: add binding for MT8365 SoC dt-bindings: display: mediatek: dither: add binding for MT8365 SoC dt-bindings: display: mediatek: dsi: add binding for MT8365 SoC dt-bindings: display: mediatek: gamma: add binding for MT8365 SoC dt-bindings: display: mediatek: ovl: add binding for MT8365 SoC dt-bindings: display: mediatek: rdma: add binding for MT8365 SoC dt-bindings: pwm: add power-domains property dt-bindings: pwm: add binding for mt8365 SoC drm/mediatek: dsi: Improves the DSI lane setup robustness arm64: defconfig: enable display connector support arm64: dts: mediatek: add display blocks support for the MT8365 SoC arm64: dts: mediatek: add display support for mt8365-evk Fabien Parent (4): dt-bindings: display: mediatek: dpi: add power-domains property dt-bindings: display: mediatek: dpi: add binding for MT8365 drm/mediatek: dpi: add support for dpi clock drm/mediatek: add MT8365 SoC support .../bindings/display/mediatek/mediatek,aal.yaml | 1 + .../bindings/display/mediatek/mediatek,ccorr.yaml | 3 + .../bindings/display/mediatek/mediatek,color.yaml | 1 + .../bindings/display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,dpi.yaml | 24 +++ .../bindings/display/mediatek/mediatek,dsi.yaml | 2 + .../bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 9 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 183 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 ++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/gpu/drm/mediatek/mtk_dpi.c | 50 +++++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 2 + 16 files changed, 455 insertions(+), 1 deletion(-) --- base-commit: d27bed55ce32b0732ef65561851fec3dc8d01852 change-id: 20231023-display-support-c6418b30e419 Best regards,