| Message ID | 20231016051102.1180432-1-thippeswamy.havalige@amd.com |
|---|---|
| Headers | show |
| Series | increase ecam size value to discover 256 buses during | expand |
Hi Bjorn, Can you please provide an update on this patch series. Regards, Thippeswamy H > -----Original Message----- > From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > Sent: Monday, October 16, 2023 10:41 AM > To: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > robh@kernel.org; krzysztof.kozlowski+dt@linaro.org; colnor+dt@kernel.org; > Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; Simek, Michal > <michal.simek@amd.com>; Gogada, Bharat Kumar > <bharat.kumar.gogada@amd.com> > Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 > buses during > > Current driver is supports up to 16 buses. The following code fixes to support > up to 256 buses. > > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM > region to detect 256 buses. > > Update ecam size to 256MB in device tree binding example. > > Remove unwanted code. > > Thippeswamy Havalige (4): > PCI: xilinx-nwl: Remove unnecessary code which updates primary, > secondary and sub-ordinate bus numbers > dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example > PCI: xilinx-nwl: Rename ECAM size default macro > PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- > drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++--------------- > 2 files changed, 4 insertions(+), 16 deletions(-) > > -- > 2.25.1
On Fri, Oct 20, 2023 at 10:35:46AM +0000, Havalige, Thippeswamy wrote: > Hi Bjorn, > > Can you please provide an update on this patch series. As with your Xilinx XDMA Soft IP series, I hope to get this merged for v6.7. Would you take a quick look at patchwork here: https://patchwork.kernel.org/project/linux-pci/list/?submitter=207519 to make sure that everything you're waiting on is listed there? I cleaned out things that appeared to be older versions of the "Increase ECAM size" and the "Add support for Xilinx XDMA Soft IP" series, but the subject lines didn't always match exactly, so it's possible I incorrectly marked something as "superseded". Bjorn > > -----Original Message----- > > From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > > Sent: Monday, October 16, 2023 10:41 AM > > To: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org > > Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > > robh@kernel.org; krzysztof.kozlowski+dt@linaro.org; colnor+dt@kernel.org; > > Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; Simek, Michal > > <michal.simek@amd.com>; Gogada, Bharat Kumar > > <bharat.kumar.gogada@amd.com> > > Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 > > buses during > > > > Current driver is supports up to 16 buses. The following code fixes to support > > up to 256 buses. > > > > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM > > region to detect 256 buses. > > > > Update ecam size to 256MB in device tree binding example. > > > > Remove unwanted code. > > > > Thippeswamy Havalige (4): > > PCI: xilinx-nwl: Remove unnecessary code which updates primary, > > secondary and sub-ordinate bus numbers > > dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example > > PCI: xilinx-nwl: Rename ECAM size default macro > > PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses > > > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- > > drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++--------------- > > 2 files changed, 4 insertions(+), 16 deletions(-) > > > > -- > > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Bjorn, Thanks for update, provided list consist of all submitted patches for both the series. Regards, Thippeswamy H > -----Original Message----- > From: Bjorn Helgaas <helgaas@kernel.org> > Sent: Monday, October 23, 2023 10:57 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > robh@kernel.org; krzysztof.kozlowski+dt@linaro.org; Simek, Michal > <michal.simek@amd.com>; Gogada, Bharat Kumar > <bharat.kumar.gogada@amd.com> > Subject: Re: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 > buses during > > On Fri, Oct 20, 2023 at 10:35:46AM +0000, Havalige, Thippeswamy wrote: > > Hi Bjorn, > > > > Can you please provide an update on this patch series. > > As with your Xilinx XDMA Soft IP series, I hope to get this merged for v6.7. > > Would you take a quick look at patchwork here: > https://patchwork.kernel.org/project/linux-pci/list/?submitter=207519 > to make sure that everything you're waiting on is listed there? > > I cleaned out things that appeared to be older versions of the "Increase ECAM > size" and the "Add support for Xilinx XDMA Soft IP" > series, but the subject lines didn't always match exactly, so it's possible I > incorrectly marked something as "superseded". > > Bjorn > > > > -----Original Message----- > > > From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > > > Sent: Monday, October 16, 2023 10:41 AM > > > To: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > > > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org > > > Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > > > robh@kernel.org; krzysztof.kozlowski+dt@linaro.org; > > > colnor+dt@kernel.org; Havalige, Thippeswamy > > > <thippeswamy.havalige@amd.com>; Simek, Michal > > > <michal.simek@amd.com>; Gogada, Bharat Kumar > > > <bharat.kumar.gogada@amd.com> > > > Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover > > > 256 buses during > > > > > > Current driver is supports up to 16 buses. The following code fixes > > > to support up to 256 buses. > > > > > > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB > ECAM > > > region to detect 256 buses. > > > > > > Update ecam size to 256MB in device tree binding example. > > > > > > Remove unwanted code. > > > > > > Thippeswamy Havalige (4): > > > PCI: xilinx-nwl: Remove unnecessary code which updates primary, > > > secondary and sub-ordinate bus numbers > > > dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example > > > PCI: xilinx-nwl: Rename ECAM size default macro > > > PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses > > > > > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- > > > drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++--------------- > > > 2 files changed, 4 insertions(+), 16 deletions(-) > > > > > > -- > > > 2.25.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hello, > Current driver is supports up to 16 buses. The following code fixes > to support up to 256 buses. > > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM > region to detect 256 buses. > > Update ecam size to 256MB in device tree binding example. > > Remove unwanted code. Applied to controller/xilinx-ecam, thank you! [01/04] PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields https://git.kernel.org/pci/pci/c/a2492ff1fcb9 [02/04] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example https://git.kernel.org/pci/pci/c/22f38a244273 [03/04] PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro https://git.kernel.org/pci/pci/c/177692115f6f [04/04] PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses https://git.kernel.org/pci/pci/c/2fccd11518f1 Krzysztof
Current driver is supports up to 16 buses. The following code fixes to support up to 256 buses. update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM region to detect 256 buses. Update ecam size to 256MB in device tree binding example. Remove unwanted code. Thippeswamy Havalige (4): PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example PCI: xilinx-nwl: Rename ECAM size default macro PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++--------------- 2 files changed, 4 insertions(+), 16 deletions(-)