Message ID | 20231020065401.1086359-1-hongtao.liu@intel.com |
---|---|
State | New |
Headers | show |
Series | [x86] Remove unused mmx_pinsrw. | expand |
On Fri, Oct 20, 2023 at 8:54 AM liuhongt <hongtao.liu@intel.com> wrote: > > When I'm working on enable more 32/64-bit vectorization for _Float16, > I notice there's 1 redundant define_expand, the patch removed the expander. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > gcc/ChangeLog: > > * config/i386/mmx.md (mmx_pinsrw): Removed. Please use present tense in the ChangeLog (like, you are commanding what to do here). OK. Thanks, Uros. > --- > gcc/config/i386/mmx.md | 14 -------------- > 1 file changed, 14 deletions(-) > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 491a0a51272..d1e1f733566 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -4574,20 +4574,6 @@ (define_insn "*mmx_pinsrd" > (set_attr "prefix" "orig,vex") > (set_attr "mode" "TI")]) > > -(define_expand "mmx_pinsrw" > - [(set (match_operand:V4HI 0 "register_operand") > - (vec_merge:V4HI > - (vec_duplicate:V4HI > - (match_operand:SI 2 "nonimmediate_operand")) > - (match_operand:V4HI 1 "register_operand") > - (match_operand:SI 3 "const_0_to_3_operand")))] > - "(TARGET_MMX || TARGET_MMX_WITH_SSE) > - && (TARGET_SSE || TARGET_3DNOW_A)" > -{ > - operands[2] = gen_lowpart (HImode, operands[2]); > - operands[3] = GEN_INT (1 << INTVAL (operands[3])); > -}) > - > (define_insn "*mmx_pinsrw" > [(set (match_operand:V4HI 0 "register_operand" "=y,x,YW") > (vec_merge:V4HI > -- > 2.31.1 >
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 491a0a51272..d1e1f733566 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -4574,20 +4574,6 @@ (define_insn "*mmx_pinsrd" (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_expand "mmx_pinsrw" - [(set (match_operand:V4HI 0 "register_operand") - (vec_merge:V4HI - (vec_duplicate:V4HI - (match_operand:SI 2 "nonimmediate_operand")) - (match_operand:V4HI 1 "register_operand") - (match_operand:SI 3 "const_0_to_3_operand")))] - "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A)" -{ - operands[2] = gen_lowpart (HImode, operands[2]); - operands[3] = GEN_INT (1 << INTVAL (operands[3])); -}) - (define_insn "*mmx_pinsrw" [(set (match_operand:V4HI 0 "register_operand" "=y,x,YW") (vec_merge:V4HI