[V5,1/2] rs6000: optimize moving to sf from highpart di

Hi,

Currently, we have the pattern "movsf_from_si2" which was trying
to support moving high part DI to SF.

But current pattern only accepts "ashiftrt":
XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
also be ok.
And current pattern only supports BE.

This patch updats the pattern to support BE and "lshiftrt".

Compare with previous version:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
This version refines the code slightly and updates the test case
according to review comments.

Pass bootstrap and regtest on ppc64{,le}.
Is this ok for trunk?

BR,
Jeff (Jiufu Guo)

	PR target/108338

gcc/ChangeLog:

	* config/rs6000/predicates.md (lowpart_subreg_operator): New
	define_predicate.
	* config/rs6000/rs6000.md (any_rshift): New code_iterator.
	(movsf_from_si2): Rename to ...
	(movsf_from_si2_<code>): ... this.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr108338.c: New test.

---
 gcc/config/rs6000/predicates.md             |  5 +++
 gcc/config/rs6000/rs6000.md                 | 12 ++++---
 gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
 3 files changed, 49 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c

On Thu, Oct 5, 2023 at 12:50 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:

> Hi,
>
> Currently, we have the pattern "movsf_from_si2" which was trying
> to support moving high part DI to SF.
>
> But current pattern only accepts "ashiftrt":
> XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
> also be ok.
> And current pattern only supports BE.
>
> This patch updats the pattern to support BE and "lshiftrt".
>
> Compare with previous version:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
> This version refines the code slightly and updates the test case
> according to review comments.
>
> Pass bootstrap and regtest on ppc64{,le}.
> Is this ok for trunk?
>

Okay.

Thanks, David


>
> BR,
> Jeff (Jiufu Guo)
>
>         PR target/108338
>
> gcc/ChangeLog:
>
>         * config/rs6000/predicates.md (lowpart_subreg_operator): New
>         define_predicate.
>         * config/rs6000/rs6000.md (any_rshift): New code_iterator.
>         (movsf_from_si2): Rename to ...
>         (movsf_from_si2_<code>): ... this.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/powerpc/pr108338.c: New test.
>
> ---
>  gcc/config/rs6000/predicates.md             |  5 +++
>  gcc/config/rs6000/rs6000.md                 | 12 ++++---
>  gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
>  3 files changed, 49 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c
>
> diff --git a/gcc/config/rs6000/predicates.md
> b/gcc/config/rs6000/predicates.md
> index 925f69cd3fc..ef7d3f214c4 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -2098,3 +2098,8 @@ (define_predicate "macho_pic_address"
>    else
>      return false;
>  })
> +
> +(define_predicate "lowpart_subreg_operator"
> +  (and (match_code "subreg")
> +       (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG
> (op)))
> +                   == SUBREG_BYTE (op)")))
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 1a9a7b1a479..56bd8bc1147 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -643,6 +643,9 @@ (define_code_iterator any_extend    [sign_extend
> zero_extend])
>  (define_code_iterator any_fix          [fix unsigned_fix])
>  (define_code_iterator any_float                [float unsigned_float])
>
> +; Shift right.
> +(define_code_iterator any_shiftrt      [ashiftrt lshiftrt])
> +
>  (define_code_attr u  [(sign_extend     "")
>                       (zero_extend      "u")
>                       (fix              "")
> @@ -8303,14 +8306,13 @@ (define_insn_and_split "movsf_from_si"
>  ;;     {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
>  ;; split it before reload with "and mask" to avoid generating shift right
>  ;; 32 bit then shift left 32 bit.
> -(define_insn_and_split "movsf_from_si2"
> +(define_insn_and_split "movsf_from_si2_<code>"
>    [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
>             (unspec:SF
> -            [(subreg:SI
> -              (ashiftrt:DI
> +            [(match_operator:SI 3 "lowpart_subreg_operator"
> +              [(any_shiftrt:DI
>                 (match_operand:DI 1 "input_operand" "r")
> -               (const_int 32))
> -              0)]
> +               (const_int 32))])]
>              UNSPEC_SF_FROM_SI))
>    (clobber (match_scratch:DI 2 "=r"))]
>    "TARGET_NO_SF_SUBREG"
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c
> b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> new file mode 100644
> index 00000000000..bd83c0b3ad8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> @@ -0,0 +1,37 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target hard_float } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +
> +struct di_sf_sf
> +{
> +  float f1; float f2; long long l;
> +};
> +
> +float __attribute__ ((noipa))
> +sf_from_high32bit_di (struct di_sf_sf v)
> +{
> +#ifdef __LITTLE_ENDIAN__
> +  return v.f2;
> +#else
> +  return v.f1;
> +#endif
> +}
> +
> +int main()
> +{
> +  struct di_sf_sf v;
> +  v.f1 = v.f2 = 0.0f;
> +#ifdef __LITTLE_ENDIAN__
> +  v.f2 = 2.0f;
> +#else
> +  v.f1 = 2.0f;
> +#endif
> +  if (sf_from_high32bit_di (v) != 2.0f)
> +    __builtin_abort ();
> +  return 0;
> +}
> --
> 2.25.1
>
>

Hi,

David Edelsohn <dje.gcc@gmail.com> writes:
>  
> On Thu, Oct 5, 2023 at 12:50 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:
>
>  Hi,
>
>  Currently, we have the pattern "movsf_from_si2" which was trying
>  to support moving high part DI to SF.
>
>  But current pattern only accepts "ashiftrt":
>  XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
>  also be ok.
>  And current pattern only supports BE.
>
>  This patch updats the pattern to support BE and "lshiftrt".
>
>  Compare with previous version:
>  https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
>  This version refines the code slightly and updates the test case
>  according to review comments.
>
>  Pass bootstrap and regtest on ppc64{,le}.
>  Is this ok for trunk?
>
> Okay.

Thank you! Committed as r14-4444.

BR,
Jeff.

>
> Thanks, David
>  
>  
>  BR,
>  Jeff (Jiufu Guo)
>
>          PR target/108338
>
>  gcc/ChangeLog:
>
>          * config/rs6000/predicates.md (lowpart_subreg_operator): New
>          define_predicate.
>          * config/rs6000/rs6000.md (any_rshift): New code_iterator.
>          (movsf_from_si2): Rename to ...
>          (movsf_from_si2_<code>): ... this.
>
>  gcc/testsuite/ChangeLog:
>
>          * gcc.target/powerpc/pr108338.c: New test.
>
>  ---
>   gcc/config/rs6000/predicates.md             |  5 +++
>   gcc/config/rs6000/rs6000.md                 | 12 ++++---
>   gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
>   3 files changed, 49 insertions(+), 5 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c
>
>  diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
>  index 925f69cd3fc..ef7d3f214c4 100644
>  --- a/gcc/config/rs6000/predicates.md
>  +++ b/gcc/config/rs6000/predicates.md
>  @@ -2098,3 +2098,8 @@ (define_predicate "macho_pic_address"
>     else
>       return false;
>   })
>  +
>  +(define_predicate "lowpart_subreg_operator"
>  +  (and (match_code "subreg")
>  +       (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op)))
>  +                   == SUBREG_BYTE (op)")))
>  diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
>  index 1a9a7b1a479..56bd8bc1147 100644
>  --- a/gcc/config/rs6000/rs6000.md
>  +++ b/gcc/config/rs6000/rs6000.md
>  @@ -643,6 +643,9 @@ (define_code_iterator any_extend    [sign_extend zero_extend])
>   (define_code_iterator any_fix          [fix unsigned_fix])
>   (define_code_iterator any_float                [float unsigned_float])
>
>  +; Shift right.
>  +(define_code_iterator any_shiftrt      [ashiftrt lshiftrt])
>  +
>   (define_code_attr u  [(sign_extend     "")
>                        (zero_extend      "u")
>                        (fix              "")
>  @@ -8303,14 +8306,13 @@ (define_insn_and_split "movsf_from_si"
>   ;;     {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
>   ;; split it before reload with "and mask" to avoid generating shift right
>   ;; 32 bit then shift left 32 bit.
>  -(define_insn_and_split "movsf_from_si2"
>  +(define_insn_and_split "movsf_from_si2_<code>"
>     [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
>              (unspec:SF
>  -            [(subreg:SI
>  -              (ashiftrt:DI
>  +            [(match_operator:SI 3 "lowpart_subreg_operator"
>  +              [(any_shiftrt:DI
>                  (match_operand:DI 1 "input_operand" "r")
>  -               (const_int 32))
>  -              0)]
>  +               (const_int 32))])]
>               UNSPEC_SF_FROM_SI))
>     (clobber (match_scratch:DI 2 "=r"))]
>     "TARGET_NO_SF_SUBREG"
>  diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
>  new file mode 100644
>  index 00000000000..bd83c0b3ad8
>  --- /dev/null
>  +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
>  @@ -0,0 +1,37 @@
>  +/* { dg-do run } */
>  +/* { dg-require-effective-target hard_float } */
>  +/* { dg-options "-O2 -save-temps" } */
>  +
>  +/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
>  +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
>  +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
>  +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
>  +
>  +struct di_sf_sf
>  +{
>  +  float f1; float f2; long long l;
>  +};
>  +
>  +float __attribute__ ((noipa))
>  +sf_from_high32bit_di (struct di_sf_sf v)
>  +{
>  +#ifdef __LITTLE_ENDIAN__
>  +  return v.f2;
>  +#else
>  +  return v.f1;
>  +#endif
>  +}
>  +
>  +int main()
>  +{
>  +  struct di_sf_sf v;
>  +  v.f1 = v.f2 = 0.0f;
>  +#ifdef __LITTLE_ENDIAN__
>  +  v.f2 = 2.0f;
>  +#else
>  +  v.f1 = 2.0f;
>  +#endif
>  +  if (sf_from_high32bit_di (v) != 2.0f)
>  +    __builtin_abort ();
>  +  return 0;
>  +}
>  -- 
>  2.25.1