| Message ID | 20231004061214.17176-1-niravkumar.l.rabara@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml | expand |
Hello, niravkumar.l.rabara@intel.com wrote on Wed, 4 Oct 2023 14:12:14 +0800: > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > Convert cadence-nand-controller.txt to yaml format. Looks good to me, one question below. > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > --- > .../devicetree/bindings/mtd/cadence,nand.yaml | 73 +++++++++++++++++++ > .../bindings/mtd/cadence-nand-controller.txt | 53 -------------- > 2 files changed, 73 insertions(+), 53 deletions(-) > create mode 100644 Documentation/devicetree/bindings/mtd/cadence,nand.yaml > delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > diff --git a/Documentation/devicetree/bindings/mtd/cadence,nand.yaml b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > new file mode 100644 > index 000000000000..781812ac702f > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence NAND controller > + > +maintainers: > + - Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > + > +allOf: > + - $ref: nand-controller.yaml > + > +properties: > + compatible: > + items: > + - const: cdns,hp-nfc > + > + reg: > + items: > + - description: Address and length of the controller register set > + - description: Address and length of the Slave DMA data port > + > + reg-names: > + items: > + - const: reg > + - const: sdma > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + dmas: > + maxItems: 1 > + > + cdns,board-delay-ps: > + description: | > + Estimated Board delay. The value includes the total round trip > + delay for the signals and is used for deciding on values associated > + with data read capture. The example formula for SDR mode is the > + following. > + board delay = RE#PAD delay + PCB trace to device + PCB trace from device > + + DQ PAD delay > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + nand-controller@10b80000 { > + compatible = "cdns,hp-nfc"; > + reg = <0x10b80000 0x10000>, > + <0x10840000 0x10000>; > + reg-names = "reg", "sdma"; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <0 97 4>; > + clocks = <&nf_clk>; > + cdns,board-delay-ps = <4830>; > + > + nand@0 { > + reg = <0>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > deleted file mode 100644 > index d2eada5044b2..000000000000 > --- a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > +++ /dev/null > @@ -1,53 +0,0 @@ > -* Cadence NAND controller > - > -Required properties: > - - compatible : "cdns,hp-nfc" > - - reg : Contains two entries, each of which is a tuple consisting of a > - physical address and length. The first entry is the address and > - length of the controller register set. The second entry is the > - address and length of the Slave DMA data port. > - - reg-names: should contain "reg" and "sdma" > - - #address-cells: should be 1. The cell encodes the chip select connection. > - - #size-cells : should be 0. > - - interrupts : The interrupt number. > - - clocks: phandle of the controller core clock (nf_clk). > - > -Optional properties: > - - dmas: shall reference DMA channel associated to the NAND controller > - - cdns,board-delay-ps : Estimated Board delay. The value includes the total > - round trip delay for the signals and is used for deciding on values > - associated with data read capture. The example formula for SDR mode is > - the following: > - board delay = RE#PAD delay + PCB trace to device + PCB trace from device > - + DQ PAD delay > - > -Child nodes represent the available NAND chips. This is not fully pictured in the current schema, by referencing nand-controller.yaml I believe you allow all kind of direct partitioning (which is legacy, and not supposed to be supported here). Can you try to define a partition directly within the controller node in the example and see whether it still passes the checks? Thanks, Miquèl
> -----Original Message----- > From: Miquel Raynal <miquel.raynal@bootlin.com> > Sent: Wednesday, October 4, 2023 3:45 PM > To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com> > Cc: Richard Weinberger <richard@nod.at>; Vignesh Raghavendra > <vigneshr@ti.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley <conor+dt@kernel.org>; > linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH] dt-bindings: mtd: cadence: convert cadence-nand- > controller.txt to yaml > > Hello, > > niravkumar.l.rabara@intel.com wrote on Wed, 4 Oct 2023 14:12:14 +0800: > > > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > > > Convert cadence-nand-controller.txt to yaml format. > > Looks good to me, one question below. > > > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > --- > > .../devicetree/bindings/mtd/cadence,nand.yaml | 73 > > +++++++++++++++++++ .../bindings/mtd/cadence-nand-controller.txt | > > 53 -------------- > > 2 files changed, 73 insertions(+), 53 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/mtd/cadence,nand.yaml > > delete mode 100644 > > Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > > > diff --git a/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > > b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > > new file mode 100644 > > index 000000000000..781812ac702f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > > @@ -0,0 +1,73 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Cadence NAND controller > > + > > +maintainers: > > + - Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > + > > +allOf: > > + - $ref: nand-controller.yaml > > + > > +properties: > > + compatible: > > + items: > > + - const: cdns,hp-nfc > > + > > + reg: > > + items: > > + - description: Address and length of the controller register set > > + - description: Address and length of the Slave DMA data port > > + > > + reg-names: > > + items: > > + - const: reg > > + - const: sdma > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + dmas: > > + maxItems: 1 > > + > > + cdns,board-delay-ps: > > + description: | > > + Estimated Board delay. The value includes the total round trip > > + delay for the signals and is used for deciding on values associated > > + with data read capture. The example formula for SDR mode is the > > + following. > > + board delay = RE#PAD delay + PCB trace to device + PCB trace from device > > + + DQ PAD delay > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - interrupts > > + - clocks > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + nand-controller@10b80000 { > > + compatible = "cdns,hp-nfc"; > > + reg = <0x10b80000 0x10000>, > > + <0x10840000 0x10000>; > > + reg-names = "reg", "sdma"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + interrupts = <0 97 4>; > > + clocks = <&nf_clk>; > > + cdns,board-delay-ps = <4830>; > > + > > + nand@0 { > > + reg = <0>; > > + }; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > deleted file mode 100644 > > index d2eada5044b2..000000000000 > > --- > > a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > +++ /dev/null > > @@ -1,53 +0,0 @@ > > -* Cadence NAND controller > > - > > -Required properties: > > - - compatible : "cdns,hp-nfc" > > - - reg : Contains two entries, each of which is a tuple consisting of a > > - physical address and length. The first entry is the address and > > - length of the controller register set. The second entry is the > > - address and length of the Slave DMA data port. > > - - reg-names: should contain "reg" and "sdma" > > - - #address-cells: should be 1. The cell encodes the chip select connection. > > - - #size-cells : should be 0. > > - - interrupts : The interrupt number. > > - - clocks: phandle of the controller core clock (nf_clk). > > - > > -Optional properties: > > - - dmas: shall reference DMA channel associated to the NAND > > controller > > - - cdns,board-delay-ps : Estimated Board delay. The value includes the total > > - round trip delay for the signals and is used for deciding on values > > - associated with data read capture. The example formula for SDR mode is > > - the following: > > - board delay = RE#PAD delay + PCB trace to device + PCB trace from device > > - + DQ PAD delay > > - > > -Child nodes represent the available NAND chips. > > This is not fully pictured in the current schema, by referencing nand- > controller.yaml I believe you allow all kind of direct partitioning (which is legacy, > and not supposed to be supported here). > Can you try to define a partition directly within the controller node in the example > and see whether it still passes the checks? > > Thanks, > Miquèl Hi Miquel, I tried below in the controller node in example, ... clocks = <&nf_clk>; cdns,board-delay-ps = <4830>; partition@0 { label = "boot"; reg = <0 0x00200000>; }; nand@0 { reg = <0>; }; It shows 'partition@0' was unexpected. DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb Documentation/devicetree/bindings/mtd/cadence,nand.example.dts:35.23-38.14: Warning (unique_unit_address_if_enabled): /example-0/nand-controller@10b80000/partition@0: duplicate unit-address (also used in node /example-0/nand-controller@10b80000/nand@0) /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb: nand-controller@10b80000: Unevaluated properties are not allowed ('partition@0' was unexpected) From schema: /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.yaml However using partition in nand node is OK. nand@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "boot"; reg = <0 0x00200000>; }; partition@200000 { label = "env"; reg = <0x00200000 0x00400000>; }; }; "make dt_binding_check DT_SCHEMA_FILES=mtd/cadence,nand.yaml" is OK without any warnings. DTEX Documentation/devicetree/bindings/mtd/cadence,nand.example.dts DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb Any additional changes required for this patch? Thanks, Nirav
Hello, > > > -Child nodes represent the available NAND chips. > > > > This is not fully pictured in the current schema, by referencing nand- > > controller.yaml I believe you allow all kind of direct partitioning (which is legacy, > > and not supposed to be supported here). > > Can you try to define a partition directly within the controller node in the example > > and see whether it still passes the checks? > > > > Thanks, > > Miquèl > > Hi Miquel, > > I tried below in the controller node in example, > > ... > clocks = <&nf_clk>; > cdns,board-delay-ps = <4830>; > > partition@0 { > label = "boot"; > reg = <0 0x00200000>; > }; > > nand@0 { > reg = <0>; > }; > > It shows 'partition@0' was unexpected. > > DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb > Documentation/devicetree/bindings/mtd/cadence,nand.example.dts:35.23-38.14: Warning (unique_unit_address_if_enabled): /example-0/nand-controller@10b80000/partition@0: duplicate unit-address (also used in node /example-0/nand-controller@10b80000/nand@0) > /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb: nand-controller@10b80000: Unevaluated properties are not allowed ('partition@0' was unexpected) > From schema: /mnt/newvolume/users/nrabara/kernel.org/3oct23/Documentation/devicetree/bindings/mtd/cadence,nand.yaml > > However using partition in nand node is OK. > nand@0 { > reg = <0>; > > #address-cells = <1>; > #size-cells = <1>; > > partition@0 { > label = "boot"; > reg = <0 0x00200000>; > }; > > partition@200000 { > label = "env"; > reg = <0x00200000 0x00400000>; > }; > }; > > "make dt_binding_check DT_SCHEMA_FILES=mtd/cadence,nand.yaml" is OK without any warnings. > > DTEX Documentation/devicetree/bindings/mtd/cadence,nand.example.dts > DTC_CHK Documentation/devicetree/bindings/mtd/cadence,nand.example.dtb > > Any additional changes required for this patch? No, should be fine then. Thanks, Miquèl
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on mtd/mtd/next]
[also build test WARNING on mtd/mtd/fixes robh/for-next linus/master v6.6-rc4 next-20231004]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/niravkumar-l-rabara-intel-com/dt-bindings-mtd-cadence-convert-cadence-nand-controller-txt-to-yaml/20231004-141601
base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/next
patch link: https://lore.kernel.org/r/20231004061214.17176-1-niravkumar.l.rabara%40intel.com
patch subject: [PATCH] dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml
reproduce: (https://download.01.org/0day-ci/archive/20231005/202310051014.XuwY3fGK-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310051014.XuwY3fGK-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence,nand.yaml b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml new file mode 100644 index 000000000000..781812ac702f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence NAND controller + +maintainers: + - Niravkumar L Rabara <niravkumar.l.rabara@intel.com> + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + items: + - const: cdns,hp-nfc + + reg: + items: + - description: Address and length of the controller register set + - description: Address and length of the Slave DMA data port + + reg-names: + items: + - const: reg + - const: sdma + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 1 + + cdns,board-delay-ps: + description: | + Estimated Board delay. The value includes the total round trip + delay for the signals and is used for deciding on values associated + with data read capture. The example formula for SDR mode is the + following. + board delay = RE#PAD delay + PCB trace to device + PCB trace from device + + DQ PAD delay + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + nand-controller@10b80000 { + compatible = "cdns,hp-nfc"; + reg = <0x10b80000 0x10000>, + <0x10840000 0x10000>; + reg-names = "reg", "sdma"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 97 4>; + clocks = <&nf_clk>; + cdns,board-delay-ps = <4830>; + + nand@0 { + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt deleted file mode 100644 index d2eada5044b2..000000000000 --- a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Cadence NAND controller - -Required properties: - - compatible : "cdns,hp-nfc" - - reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the Slave DMA data port. - - reg-names: should contain "reg" and "sdma" - - #address-cells: should be 1. The cell encodes the chip select connection. - - #size-cells : should be 0. - - interrupts : The interrupt number. - - clocks: phandle of the controller core clock (nf_clk). - -Optional properties: - - dmas: shall reference DMA channel associated to the NAND controller - - cdns,board-delay-ps : Estimated Board delay. The value includes the total - round trip delay for the signals and is used for deciding on values - associated with data read capture. The example formula for SDR mode is - the following: - board delay = RE#PAD delay + PCB trace to device + PCB trace from device - + DQ PAD delay - -Child nodes represent the available NAND chips. - -Required properties of NAND chips: - - reg: shall contain the native Chip Select ids from 0 to max supported by - the cadence nand flash controller - -See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on -generic bindings. - -Example: - -nand_controller: nand-controller@60000000 { - compatible = "cdns,hp-nfc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60000000 0x10000>, <0x80000000 0x10000>; - reg-names = "reg", "sdma"; - clocks = <&nf_clk>; - cdns,board-delay-ps = <4830>; - interrupts = <2 0>; - nand@0 { - reg = <0>; - label = "nand-1"; - }; - nand@1 { - reg = <1>; - label = "nand-2"; - }; - -};