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[V1] RISC-V: Fix a bug that causes an error insn.

Message ID 20230808041232.15387-1-shiyulong@iscas.ac.cn
State New
Headers show
Series [V1] RISC-V: Fix a bug that causes an error insn. | expand

Commit Message

yulong Aug. 8, 2023, 4:12 a.m. UTC 
From: yulong <shiyulong@iscas.ac.cn>

I test the following rvv intrinsics.
vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);}
And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 日 [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 日 zero)] UNSPEC_VUNDEF)
(reg/v:RVVMF64BI 137 [ mask ]))
(unspec:RVVM1DI[(reg:sI 日 zero)] UNSPEC_VUNDEF)))

This patch fix it.

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
        * gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
        * gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
        * gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
        * gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
        * gcc.target/riscv/rvv/base/vslide1up-3.c: New test.

---
 gcc/config/riscv/riscv-v.cc                   |  5 ++---
 .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-1.c   | 22 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-2.c   | 22 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-3.c   | 22 +++++++++++++++++++
 7 files changed, 134 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c

Comments

Kito Cheng Aug. 8, 2023, 7:40 a.m. UTC | #1 
OK for trunk and GCC 13 :)

On Tue, Aug 8, 2023 at 2:46 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Thanks for fixing it.
>
> @kito: Hi, kito. This is the bug also exists in GCC-13, can we backport to GCC-13?
>
>
>
> juzhe.zhong@rivai.ai
>
> From: shiyulong
> Date: 2023-08-08 12:12
> To: gcc-patches
> CC: kito.cheng; wuwei2016; jiawei; shihua; chenyixuan; juzhe.zhong; pan2.li; yulong
> Subject: [PATCH V1] RISC-V: Fix a bug that causes an error insn.
> From: yulong <shiyulong@iscas.ac.cn>
>
> I test the following rvv intrinsics.
> vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
>   return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);}
> And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 鏃? [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 鏃? zero)] UNSPEC_VUNDEF)
> (reg/v:RVVMF64BI 137 [ mask ]))
> (unspec:RVVM1DI[(reg:sI 鏃? zero)] UNSPEC_VUNDEF)))
>
> This patch fix it.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-3.c: New test.
>
> ---
> gcc/config/riscv/riscv-v.cc                   |  5 ++---
> .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-1.c   | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-2.c   | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-3.c   | 22 +++++++++++++++++++
> 7 files changed, 134 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 278452b9e05..f73ec8c6474 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -2103,9 +2103,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
>      CONSTM1_RTX (demote_mask_mode), merge, temp,
>      demote_scalar_op2, vl_x2, ta, ma, ops[8]));
> -  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
> -    return true;
> -  else
> +  if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
> +      && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]))))
>      emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
>        force_vector_length_operand (ops[5]), ops[6],
>        ops[8]));
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> new file mode 100644
> index 00000000000..541745be2a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> new file mode 100644
> index 00000000000..9b5a240a9e6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> new file mode 100644
> index 00000000000..7b05c85a243
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> new file mode 100644
> index 00000000000..74e8e5e63f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> new file mode 100644
> index 00000000000..e7e2ee950c7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
> new file mode 100644
> index 00000000000..b0b3af24e64
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> --
> 2.34.1
>
>
Li, Pan2 via Gcc-patches Aug. 8, 2023, 7:50 a.m. UTC | #2 
Committed to both the trunk and gcc-13, thanks Kito and Juzhe.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Tuesday, August 8, 2023 3:40 PM
To: juzhe.zhong@rivai.ai
Cc: yulong <shiyulong@iscas.ac.cn>; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; wuwei2016 <wuwei2016@iscas.ac.cn>; jiawei <jiawei@iscas.ac.cn>; shihua <shihua@iscas.ac.cn>; chenyixuan <chenyixuan@iscas.as.cn>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH V1] RISC-V: Fix a bug that causes an error insn.

OK for trunk and GCC 13 :)

On Tue, Aug 8, 2023 at 2:46 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Thanks for fixing it.
>
> @kito: Hi, kito. This is the bug also exists in GCC-13, can we backport to GCC-13?
>
>
>
> juzhe.zhong@rivai.ai
>
> From: shiyulong
> Date: 2023-08-08 12:12
> To: gcc-patches
> CC: kito.cheng; wuwei2016; jiawei; shihua; chenyixuan; juzhe.zhong; pan2.li; yulong
> Subject: [PATCH V1] RISC-V: Fix a bug that causes an error insn.
> From: yulong <shiyulong@iscas.ac.cn>
>
> I test the following rvv intrinsics.
> vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
>   return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);}
> And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 鏃? [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 鏃? zero)] UNSPEC_VUNDEF)
> (reg/v:RVVMF64BI 137 [ mask ]))
> (unspec:RVVM1DI[(reg:sI 鏃? zero)] UNSPEC_VUNDEF)))
>
> This patch fix it.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
>         * gcc.target/riscv/rvv/base/vslide1up-3.c: New test.
>
> ---
> gcc/config/riscv/riscv-v.cc                   |  5 ++---
> .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-1.c   | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-2.c   | 22 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vslide1up-3.c   | 22 +++++++++++++++++++
> 7 files changed, 134 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 278452b9e05..f73ec8c6474 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -2103,9 +2103,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
>      CONSTM1_RTX (demote_mask_mode), merge, temp,
>      demote_scalar_op2, vl_x2, ta, ma, ops[8]));
> -  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
> -    return true;
> -  else
> +  if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
> +      && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]))))
>      emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
>        force_vector_length_operand (ops[5]), ops[6],
>        ops[8]));
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> new file mode 100644
> index 00000000000..541745be2a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> new file mode 100644
> index 00000000000..9b5a240a9e6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> new file mode 100644
> index 00000000000..7b05c85a243
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> new file mode 100644
> index 00000000000..74e8e5e63f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> new file mode 100644
> index 00000000000..e7e2ee950c7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
> new file mode 100644
> index 00000000000..b0b3af24e64
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
> +}
> +
> +vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
> +}
> +
> +vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
> +}
> +
> +vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
> +  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..f73ec8c6474 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2103,9 +2103,8 @@  slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
 			     CONSTM1_RTX (demote_mask_mode), merge, temp,
 			     demote_scalar_op2, vl_x2, ta, ma, ops[8]));
 
-  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
-    return true;
-  else
+  if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
+      && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]))))
     emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
 			       force_vector_length_operand (ops[5]), ops[6],
 			       ops[8]));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
new file mode 100644
index 00000000000..541745be2a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
new file mode 100644
index 00000000000..9b5a240a9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
new file mode 100644
index 00000000000..7b05c85a243
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
new file mode 100644
index 00000000000..74e8e5e63f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
new file mode 100644
index 00000000000..e7e2ee950c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
new file mode 100644
index 00000000000..b0b3af24e64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */