mbox series

[v2,0/8] mtd: spi-nor: spansion: Add support for Infineon S28HS02GT

Message ID cover.1689836065.git.Takahiro.Kuwano@infineon.com
Headers show
Series mtd: spi-nor: spansion: Add support for Infineon S28HS02GT | expand

Message

Takahiro Kuwano July 20, 2023, 7:09 a.m. UTC
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

Infineon S28HS02GT is 2Gbit, multi-chip package, Octal SPI NOR flash. This
series reworks octal_dtr_enable part to support MCP and then adds ID and
fixups for S28HS02GT.

Tested on Zynq-7000 platform with Infineon SPI controller

ID, SFDP, Test logs:
---
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
s28hs02gt
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
345b1c
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
spansion
zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450080106fe00000114000100ff84000102500100ff050001055801
00ff8700011c6c0100ff88000106dc0100ff81000118040200ff0a000104
f40100ffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
fffffffffffffffffffffffffffffffff7218affffffff7f000000000000
0000eeffffffffff0000ffff00000c2100ff00ff12dc23faff8b82e7ffec
ec2319497ab07ab0f766805c000000fff910c0a0000000000000bc020000
0000ffff7e7e41120ffe21ffffdc00ee800b7171656500b0ff9600000000
0c551ca20000800000000000c0ccfffb88fbfffb00650090066500b10065
009600650095716503d0716503d0a46bfb0290a579a20040288e0000ff00
0000ff0071650690716506900000000000000000716506d1716506d17165
0691716506910000ff000000ff00716505d5716505d50000a01500008008
000000080000801000000010000080180000001800000601000000008000
710600030600fc65ff0804008000fc65ff0402008000fc65ff0804008008
fd65ff0402008008fe0202fff1ff0100f8ff0100f8fffb0ffe0902fff8ff
fb0ff8ff0100f1ff0100fe0104fff1ff0100f8ff0100f8fff70ff8ff0100
f1ff0100ff0a00fff8ffff0f                                    
zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
6193b9729008b80b9a2b4bb3ce06a91d  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> test_qspi.sh
6+0 records in
6+0 records out
6291456 bytes (6.0MB) copied, 0.234679 seconds, 25.6MB/s
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Erased 6291456 bytes from address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0600000
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
3020d73d4d0e570449faacfbadf134e074ced30e  qspi_test
3020d73d4d0e570449faacfbadf134e074ced30e  qspi_read
---

Takahiro Kuwano (8):
  mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
  mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT
  mtd: spi-nor: spansion: prepare octal dtr methods for multi chip
    support
  mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
  mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset
  mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
  mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP
  mtd: spi-nor: spansion: add support for S28HS02GT

 drivers/mtd/spi-nor/atmel.c     |   8 +-
 drivers/mtd/spi-nor/core.c      |  23 ++--
 drivers/mtd/spi-nor/core.h      |   4 +-
 drivers/mtd/spi-nor/issi.c      |   4 +-
 drivers/mtd/spi-nor/macronix.c  |   4 +-
 drivers/mtd/spi-nor/micron-st.c |   4 +-
 drivers/mtd/spi-nor/spansion.c  | 193 ++++++++++++++++++++++++++------
 drivers/mtd/spi-nor/sst.c       |   8 +-
 drivers/mtd/spi-nor/winbond.c   |   4 +-
 drivers/mtd/spi-nor/xilinx.c    |   4 +-
 10 files changed, 201 insertions(+), 55 deletions(-)

Comments

Takahiro Kuwano July 20, 2023, 7:54 a.m. UTC | #1
Hi,

I tested with the following devices, as this series updates the code used by
other SEMPER flash devices than S28HS02GT.
 - S28HS02GT(Octal, multi-chip)
 - S28HS01GT(Octal, single-chip)
 - S25HS02GT(Quad, multi-chip)
 - S25HS01GT(Quad, single-chip)
 - S25FS256T(Quad, single-chip)

Thanks,
Takahiro

On 7/20/2023 4:09 PM, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> Infineon S28HS02GT is 2Gbit, multi-chip package, Octal SPI NOR flash. This
> series reworks octal_dtr_enable part to support MCP and then adds ID and
> fixups for S28HS02GT.
> 
> Tested on Zynq-7000 platform with Infineon SPI controller
> 
> ID, SFDP, Test logs:
> ---
> zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
> s28hs02gt
> zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
> 345b1c
> zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
> spansion
> zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
> 53464450080106fe00000114000100ff84000102500100ff050001055801
> 00ff8700011c6c0100ff88000106dc0100ff81000118040200ff0a000104
> f40100ffffffffffffffffffffffffffffffffffffffffffffffffffffff
> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
> fffffffffffffffffffffffffffffffff7218affffffff7f000000000000
> 0000eeffffffffff0000ffff00000c2100ff00ff12dc23faff8b82e7ffec
> ec2319497ab07ab0f766805c000000fff910c0a0000000000000bc020000
> 0000ffff7e7e41120ffe21ffffdc00ee800b7171656500b0ff9600000000
> 0c551ca20000800000000000c0ccfffb88fbfffb00650090066500b10065
> 009600650095716503d0716503d0a46bfb0290a579a20040288e0000ff00
> 0000ff0071650690716506900000000000000000716506d1716506d17165
> 0691716506910000ff000000ff00716505d5716505d50000a01500008008
> 000000080000801000000010000080180000001800000601000000008000
> 710600030600fc65ff0804008000fc65ff0402008000fc65ff0804008008
> fd65ff0402008008fe0202fff1ff0100f8ff0100f8fffb0ffe0902fff8ff
> fb0ff8ff0100f1ff0100fe0104fff1ff0100f8ff0100f8fff70ff8ff0100
> f1ff0100ff0a00fff8ffff0f                                    
> zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
> 6193b9729008b80b9a2b4bb3ce06a91d  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
> zynq> test_qspi.sh
> 6+0 records in
> 6+0 records out
> 6291456 bytes (6.0MB) copied, 0.234679 seconds, 25.6MB/s
> Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
> Erased 6291456 bytes from address 0x00000000 in flash
> Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> *
> 0600000
> Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
> Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
> 3020d73d4d0e570449faacfbadf134e074ced30e  qspi_test
> 3020d73d4d0e570449faacfbadf134e074ced30e  qspi_read
> ---
> 
> Takahiro Kuwano (8):
>   mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
>   mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT
>   mtd: spi-nor: spansion: prepare octal dtr methods for multi chip
>     support
>   mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
>   mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset
>   mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
>   mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP
>   mtd: spi-nor: spansion: add support for S28HS02GT
> 
>  drivers/mtd/spi-nor/atmel.c     |   8 +-
>  drivers/mtd/spi-nor/core.c      |  23 ++--
>  drivers/mtd/spi-nor/core.h      |   4 +-
>  drivers/mtd/spi-nor/issi.c      |   4 +-
>  drivers/mtd/spi-nor/macronix.c  |   4 +-
>  drivers/mtd/spi-nor/micron-st.c |   4 +-
>  drivers/mtd/spi-nor/spansion.c  | 193 ++++++++++++++++++++++++++------
>  drivers/mtd/spi-nor/sst.c       |   8 +-
>  drivers/mtd/spi-nor/winbond.c   |   4 +-
>  drivers/mtd/spi-nor/xilinx.c    |   4 +-
>  10 files changed, 201 insertions(+), 55 deletions(-)
>
Tudor Ambarus July 22, 2023, 5:04 a.m. UTC | #2
On 20.07.2023 10:54, Takahiro Kuwano wrote:
> I tested with the following devices, as this series updates the code used by
> other SEMPER flash devices than S28HS02GT.
>  - S28HS02GT(Octal, multi-chip)
>  - S28HS01GT(Octal, single-chip)
>  - S25HS02GT(Quad, multi-chip)
>  - S25HS01GT(Quad, single-chip)
>  - S25FS256T(Quad, single-chip)

That's good effort, thanks! Now that you introduced CLPEF and you have
to test all the flashes, is a good time to let SFDP determine the flash
size and let the core select the erase size. Can you please test the
following patch? You'll have to make sure that the flash size and the
selected erase size are sane.

https://lore.kernel.org/linux-mtd/20230722045901.9872-1-tudor.ambarus@linaro.org/T/#u

Thanks,
ta