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[v3,0/7] Display support for MSM8226

Message ID 20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz
Headers show
Series Display support for MSM8226 | expand

Message

Luca Weiss June 1, 2023, 5 p.m. UTC 
This series adds the required configs for MDP5 and DSI blocks that are
needed for MDSS on MSM8226. Finally we can add the new nodes into the
dts.

Tested on apq8026-lg-lenok and msm8926-htc-memul.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
Changes in v3:
- Adjust mdss labels to new style (Stephan)
- Link to v2: https://lore.kernel.org/r/20230308-msm8226-mdp-v2-0-e005b769ee28@z3ntu.xyz

Changes in v2:
- In dsi-phy-28nm.yaml fix the order of the compatibles 1/7 (Conor)
- Remove leftover debugging comments from 6/7 (Konrad)
- Rewrap some clock-names lines and move status property last in 7/7
  (Konrad)
- Pick up tags
- Link to v1: https://lore.kernel.org/r/20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz

---
Luca Weiss (7):
      dt-bindings: msm: dsi-phy-28nm: Document msm8226 compatible
      dt-bindings: display/msm: dsi-controller-main: Add msm8226 compatible
      dt-bindings: display/msm: qcom,mdp5: Add msm8226 compatible
      drm/msm/mdp5: Add MDP5 configuration for MSM8226
      drm/msm/dsi: Add configuration for MSM8226
      drm/msm/dsi: Add phy configuration for MSM8226
      ARM: dts: qcom: msm8226: Add mdss nodes

 .../bindings/display/msm/dsi-controller-main.yaml  |   2 +
 .../bindings/display/msm/dsi-phy-28nm.yaml         |   3 +-
 .../devicetree/bindings/display/msm/qcom,mdp5.yaml |   1 +
 .../devicetree/bindings/display/msm/qcom,mdss.yaml |   1 +
 arch/arm/boot/dts/qcom-msm8226.dtsi                | 127 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c           |  82 +++++++++++++
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |   2 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   3 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c         |  97 ++++++++++++++++
 11 files changed, 319 insertions(+), 2 deletions(-)
---
base-commit: 1b3183710d69a48baf728cc1bee9f1fb3cfeb507
change-id: 20230308-msm8226-mdp-6431e8d672a0

Best regards,

Comments

Dmitry Baryshkov June 4, 2023, 2:39 a.m. UTC | #1 
On 01/06/2023 20:00, Luca Weiss wrote:
> MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
> based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
> 
> Worth noting that the msm-3.10 downstream kernel also will try other
> sequences in case this one doesn't work, but during testing it has shown
> that the _m sequence succeeds first time also:
> 
>    .pll_enable_seqs[0] = dsi_pll_enable_seq_m,
>    .pll_enable_seqs[1] = dsi_pll_enable_seq_m,
>    .pll_enable_seqs[2] = dsi_pll_enable_seq_d,
>    .pll_enable_seqs[3] = dsi_pll_enable_seq_d,
>    .pll_enable_seqs[4] = dsi_pll_enable_seq_f1,
>    .pll_enable_seqs[5] = dsi_pll_enable_seq_c,
>    .pll_enable_seqs[6] = dsi_pll_enable_seq_e,
> 
> We may need to expand this in the future.
> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c      |  2 +
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h      |  3 +-
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++
>   3 files changed, 101 insertions(+), 1 deletion(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov June 4, 2023, 3:01 a.m. UTC | #2 
On Thu, 01 Jun 2023 19:00:07 +0200, Luca Weiss wrote:
> This series adds the required configs for MDP5 and DSI blocks that are
> needed for MDSS on MSM8226. Finally we can add the new nodes into the
> dts.
> 
> Tested on apq8026-lg-lenok and msm8926-htc-memul.
> 
> 
> [...]

Applied, thanks!

[1/7] dt-bindings: msm: dsi-phy-28nm: Document msm8226 compatible
      https://gitlab.freedesktop.org/lumag/msm/-/commit/d01eb3421b10
[2/7] dt-bindings: display/msm: dsi-controller-main: Add msm8226 compatible
      https://gitlab.freedesktop.org/lumag/msm/-/commit/46ccf3e0ed63
[3/7] dt-bindings: display/msm: qcom,mdp5: Add msm8226 compatible
      https://gitlab.freedesktop.org/lumag/msm/-/commit/c6e79fd5c80d
[4/7] drm/msm/mdp5: Add MDP5 configuration for MSM8226
      https://gitlab.freedesktop.org/lumag/msm/-/commit/eed3f9c7c36a
[5/7] drm/msm/dsi: Add configuration for MSM8226
      https://gitlab.freedesktop.org/lumag/msm/-/commit/82cf4954a0d5
[6/7] drm/msm/dsi: Add phy configuration for MSM8226
      https://gitlab.freedesktop.org/lumag/msm/-/commit/1531d0b9235e

Best regards,
Jeykumar Sankaran June 6, 2023, 7:44 p.m. UTC | #3 
On 6/1/2023 10:00 AM, Luca Weiss wrote:
> Add the required config for the v1.1 MDP5 found on MSM8226.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>   drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82 ++++++++++++++++++++++++++++++++
>   1 file changed, 82 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> index 2eec2d78f32a..694d54341337 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> @@ -103,6 +103,87 @@ static const struct mdp5_cfg_hw msm8x74v1_config = {
>   	.max_clk = 200000000,
>   };
>   
> +static const struct mdp5_cfg_hw msm8x26_config = {
> +	.name = "msm8x26",
> +	.mdp = {
> +		.count = 1,
> +		.caps = MDP_CAP_SMP |
> +			0,
> +	},
> +	.smp = {
> +		.mmb_count = 7,
> +		.mmb_size = 4096,
> +		.clients = {
> +			[SSPP_VIG0] =  1,
> +			[SSPP_DMA0] = 4,
> +			[SSPP_RGB0] = 7,
> +		},
> +	},
> +	.ctl = {
> +		.count = 2,
> +		.base = { 0x00500, 0x00600 },
> +		.flush_hw_mask = 0x0003ffff,
> +	},
> +	.pipe_vig = {
> +		.count = 1,
> +		.base = { 0x01100 },
> +		.caps = MDP_PIPE_CAP_HFLIP |
> +			MDP_PIPE_CAP_VFLIP |
> +			MDP_PIPE_CAP_SCALE |
> +			MDP_PIPE_CAP_CSC   |
> +			0,
> +	},
> +	.pipe_rgb = {
> +		.count = 1,
> +		.base = { 0x01d00 },
> +		.caps = MDP_PIPE_CAP_HFLIP |
> +			MDP_PIPE_CAP_VFLIP |
> +			MDP_PIPE_CAP_SCALE |
> +			0,
> +	},
> +	.pipe_dma = {
> +		.count = 1,
> +		.base = { 0x02900 },
> +		.caps = MDP_PIPE_CAP_HFLIP |
> +			MDP_PIPE_CAP_VFLIP |
> +			0,
> +	},
> +	.lm = {
> +		.count = 2,
> +		.base = { 0x03100, 0x03d00 },
> +		.instances = {
> +				{ .id = 0, .pp = 0, .dspp = 0,
> +				  .caps = MDP_LM_CAP_DISPLAY, },
> +				{ .id = 1, .pp = -1, .dspp = -1,
> +				  .caps = MDP_LM_CAP_WB },
> +			     },
> +		.nb_stages = 2,
> +		.max_width = 2048,
> +		.max_height = 0xFFFF,
> +	},
> +	.dspp = {
> +		.count = 1,
> +		.base = { 0x04500 },
> +	},
> +	.pp = {
> +		.count = 1,
> +		.base = { 0x21a00 },
> +	},
> +	.intf = {
> +		.base = { 0x00000, 0x21200 },
> +		.connect = {
> +			[0] = INTF_DISABLED,
> +			[1] = INTF_DSI,
> +		},
> +	},
> +	.perf = {
> +		.ab_inefficiency = 100,
> +		.ib_inefficiency = 200,
> +		.clk_inefficiency = 125
> +	},
> +	.max_clk = 200000000,
> +};
> +
>   static const struct mdp5_cfg_hw msm8x74v2_config = {
>   	.name = "msm8x74",
>   	.mdp = {
> @@ -1236,6 +1317,7 @@ static const struct mdp5_cfg_hw sdm660_config = {
>   
>   static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
>   	{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
> +	{ .revision = 1, .config = { .hw = &msm8x26_config } },
>   	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
>   	{ .revision = 3, .config = { .hw = &apq8084_config } },
>   	{ .revision = 6, .config = { .hw = &msm8x16_config } },
> 
Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Jeykumar Sankaran June 6, 2023, 7:44 p.m. UTC | #4 
On 6/1/2023 10:00 AM, Luca Weiss wrote:
> Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
> existing bits from other revisions that are identical for v1.0.2.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>   drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
>   drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
>   2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index 29ccd755cc2e..8a5fb6df7210 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -245,6 +245,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>   		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
>   	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
>   		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2,
> +		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
>   	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
>   		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
>   	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index 91bdaf50bb1a..43f0dd74edb6 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -11,6 +11,7 @@
>   #define MSM_DSI_VER_MAJOR_V2	0x02
>   #define MSM_DSI_VER_MAJOR_6G	0x03
>   #define MSM_DSI_6G_VER_MINOR_V1_0	0x10000000
> +#define MSM_DSI_6G_VER_MINOR_V1_0_2	0x10000002
>   #define MSM_DSI_6G_VER_MINOR_V1_1	0x10010000
>   #define MSM_DSI_6G_VER_MINOR_V1_1_1	0x10010001
>   #define MSM_DSI_6G_VER_MINOR_V1_2	0x10020000
> 
Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Jeykumar Sankaran June 7, 2023, 7:46 p.m. UTC | #5 
On 6/1/2023 10:00 AM, Luca Weiss wrote:
> MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
> based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
> 
> Worth noting that the msm-3.10 downstream kernel also will try other
> sequences in case this one doesn't work, but during testing it has shown
> that the _m sequence succeeds first time also:
> 
>    .pll_enable_seqs[0] = dsi_pll_enable_seq_m,
>    .pll_enable_seqs[1] = dsi_pll_enable_seq_m,
>    .pll_enable_seqs[2] = dsi_pll_enable_seq_d,
>    .pll_enable_seqs[3] = dsi_pll_enable_seq_d,
>    .pll_enable_seqs[4] = dsi_pll_enable_seq_f1,
>    .pll_enable_seqs[5] = dsi_pll_enable_seq_c,
>    .pll_enable_seqs[6] = dsi_pll_enable_seq_e,
> 
> We may need to expand this in the future.
> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c      |  2 +
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h      |  3 +-
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++
>   3 files changed, 101 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index bb09cbe8ff86..9d5795c58a98 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>   	  .data = &dsi_phy_28nm_hpm_famb_cfgs },
>   	{ .compatible = "qcom,dsi-phy-28nm-lp",
>   	  .data = &dsi_phy_28nm_lp_cfgs },
> +	{ .compatible = "qcom,dsi-phy-28nm-8226",
> +	  .data = &dsi_phy_28nm_8226_cfgs },
>   #endif
>   #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
>   	{ .compatible = "qcom,dsi-phy-20nm",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 7137a17ae523..8b640d174785 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg {
>   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
> -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 4c1bf55c5f38..ceec7bb87bf1 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -37,6 +37,7 @@
>   
>   /* v2.0.0 28nm LP implementation */
>   #define DSI_PHY_28NM_QUIRK_PHY_LP	BIT(0)
> +#define DSI_PHY_28NM_QUIRK_PHY_8226	BIT(1)
>   
>   #define LPFR_LUT_SIZE			10
>   struct lpfr_cfg {
> @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
>   	return ret;
>   }
>   
> +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
> +{
> +	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> +	struct device *dev = &pll_28nm->phy->pdev->dev;
> +	void __iomem *base = pll_28nm->phy->pll_base;
> +	u32 max_reads = 5, timeout_us = 100;
> +	bool locked;
> +	u32 val;
> +	int i;
> +
> +	DBG("id=%d", pll_28nm->phy->id);
> +
> +	pll_28nm_software_reset(pll_28nm);
> +
> +	/*
> +	 * PLL power up sequence.
> +	 * Add necessary delays recommended by hardware.
> +	 */
> +	dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34);
> +
> +	val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> +
> +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> +
> +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> +
> +	for (i = 0; i < 7; i++) {
> +		/* DSI Uniphy lock detect setting */
> +		dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
> +				0x0c, 100);
> +		dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> +
> +		/* poll for PLL ready status */
> +		locked = pll_28nm_poll_for_ready(pll_28nm,
> +						max_reads, timeout_us);
> +		if (locked)
> +			break;
> +
> +		pll_28nm_software_reset(pll_28nm);
> +
> +		/*
> +		 * PLL power up sequence.
> +		 * Add necessary delays recommended by hardware.
> +		 */
> +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50);
> +
> +		val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100);
> +
> +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> +	}
> +
> +	if (unlikely(!locked))
> +		DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
> +	else
> +		DBG("DSI PLL Lock success");
> +
> +	return locked ? 0 : -EINVAL;
> +}
> +
Could you please share the downstream reference you used to come up with 
this sequence?

Thanks and Regards,
Jeykumar S.
>   static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
>   {
>   	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> @@ -471,6 +540,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
>   	.is_enabled = dsi_pll_28nm_clk_is_enabled,
>   };
>   
> +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = {
> +	.round_rate = dsi_pll_28nm_clk_round_rate,
> +	.set_rate = dsi_pll_28nm_clk_set_rate,
> +	.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> +	.prepare = dsi_pll_28nm_vco_prepare_8226,
> +	.unprepare = dsi_pll_28nm_vco_unprepare,
> +	.is_enabled = dsi_pll_28nm_clk_is_enabled,
> +};
> +
>   /*
>    * PLL Callbacks
>    */
> @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
>   
>   	if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>   		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> +	else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226)
> +		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226;
>   	else
>   		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
>   
> @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
>   	.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
>   };
>   
> +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = {
> +	.has_phy_regulator = true,
> +	.regulator_data = dsi_phy_28nm_regulators,
> +	.num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators),
> +	.ops = {
> +		.enable = dsi_28nm_phy_enable,
> +		.disable = dsi_28nm_phy_disable,
> +		.pll_init = dsi_pll_28nm_init,
> +		.save_pll_state = dsi_28nm_pll_save_state,
> +		.restore_pll_state = dsi_28nm_pll_restore_state,
> +	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
> +	.io_start = { 0xfd922b00 },
> +	.num_dsi_phy = 1,
> +	.quirks = DSI_PHY_28NM_QUIRK_PHY_8226,
> +};
>
Luca Weiss June 7, 2023, 9 p.m. UTC | #6 
On Mittwoch, 7. Juni 2023 21:46:31 CEST Jeykumar Sankaran wrote:
> On 6/1/2023 10:00 AM, Luca Weiss wrote:
> > MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
> > based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
> > 
> > Worth noting that the msm-3.10 downstream kernel also will try other
> > sequences in case this one doesn't work, but during testing it has shown
> > 
> > that the _m sequence succeeds first time also:
> >    .pll_enable_seqs[0] = dsi_pll_enable_seq_m,
> >    .pll_enable_seqs[1] = dsi_pll_enable_seq_m,
> >    .pll_enable_seqs[2] = dsi_pll_enable_seq_d,
> >    .pll_enable_seqs[3] = dsi_pll_enable_seq_d,
> >    .pll_enable_seqs[4] = dsi_pll_enable_seq_f1,
> >    .pll_enable_seqs[5] = dsi_pll_enable_seq_c,
> >    .pll_enable_seqs[6] = dsi_pll_enable_seq_e,
> > 
> > We may need to expand this in the future.
> > 
> > Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> > ---
> > 
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c      |  2 +
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h      |  3 +-
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97
> >   ++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 1
> >   deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index bb09cbe8ff86..9d5795c58a98
> > 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] =
> > {
> > 
> >   	  .data = &dsi_phy_28nm_hpm_famb_cfgs },
> >   	
> >   	{ .compatible = "qcom,dsi-phy-28nm-lp",
> >   	
> >   	  .data = &dsi_phy_28nm_lp_cfgs },
> > 
> > +	{ .compatible = "qcom,dsi-phy-28nm-8226",
> > +	  .data = &dsi_phy_28nm_8226_cfgs },
> > 
> >   #endif
> >   #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
> >   
> >   	{ .compatible = "qcom,dsi-phy-20nm",
> > 
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7137a17ae523..8b640d174785
> > 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg {
> > 
> >   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
> > 
> > -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
> > +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
> > 
> >   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
> > 
> > +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
> > 
> >   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
> > 
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index
> > 4c1bf55c5f38..ceec7bb87bf1 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> > @@ -37,6 +37,7 @@
> > 
> >   /* v2.0.0 28nm LP implementation */
> >   #define DSI_PHY_28NM_QUIRK_PHY_LP	BIT(0)
> > 
> > +#define DSI_PHY_28NM_QUIRK_PHY_8226	BIT(1)
> > 
> >   #define LPFR_LUT_SIZE			10
> >   struct lpfr_cfg {
> > 
> > @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw
> > *hw)> 
> >   	return ret;
> >   
> >   }
> > 
> > +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
> > +{
> > +	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> > +	struct device *dev = &pll_28nm->phy->pdev->dev;
> > +	void __iomem *base = pll_28nm->phy->pll_base;
> > +	u32 max_reads = 5, timeout_us = 100;
> > +	bool locked;
> > +	u32 val;
> > +	int i;
> > +
> > +	DBG("id=%d", pll_28nm->phy->id);
> > +
> > +	pll_28nm_software_reset(pll_28nm);
> > +
> > +	/*
> > +	 * PLL power up sequence.
> > +	 * Add necessary delays recommended by hardware.
> > +	 */
> > +	dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34);
> > +
> > +	val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> > +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> > +
> > +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> > +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> > +
> > +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> > +	val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> > +	dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> > +
> > +	for (i = 0; i < 7; i++) {
> > +		/* DSI Uniphy lock detect setting */
> > +		dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> > +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
> > +				0x0c, 100);
> > +		dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> > +
> > +		/* poll for PLL ready status */
> > +		locked = pll_28nm_poll_for_ready(pll_28nm,
> > +						max_reads, timeout_us);
> > +		if (locked)
> > +			break;
> > +
> > +		pll_28nm_software_reset(pll_28nm);
> > +
> > +		/*
> > +		 * PLL power up sequence.
> > +		 * Add necessary delays recommended by hardware.
> > +		 */
> > +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50);
> > +
> > +		val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> > +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> > +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100);
> > +
> > +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> > +		val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> > +		dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> > +	}
> > +
> > +	if (unlikely(!locked))
> > +		DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
> > +	else
> > +		DBG("DSI PLL Lock success");
> > +
> > +	return locked ? 0 : -EINVAL;
> > +}
> > +
> 
> Could you please share the downstream reference you used to come up with
> this sequence?

Hi, it should be this if I don't misremember.

https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-lenok-3.10-marshmallow-mr1-wear-release/arch/arm/mach-msm/clock-mdss-8974.c#1088

Regards
Luca

> 
> Thanks and Regards,
> Jeykumar S.
> 
> >   static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
> >   {
> >   
> >   	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> > 
> > @@ -471,6 +540,15 @@ static const struct clk_ops
> > clk_ops_dsi_pll_28nm_vco_lp = {> 
> >   	.is_enabled = dsi_pll_28nm_clk_is_enabled,
> >   
> >   };
> > 
> > +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = {
> > +	.round_rate = dsi_pll_28nm_clk_round_rate,
> > +	.set_rate = dsi_pll_28nm_clk_set_rate,
> > +	.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> > +	.prepare = dsi_pll_28nm_vco_prepare_8226,
> > +	.unprepare = dsi_pll_28nm_vco_unprepare,
> > +	.is_enabled = dsi_pll_28nm_clk_is_enabled,
> > +};
> > +
> > 
> >   /*
> >   
> >    * PLL Callbacks
> >    */
> > 
> > @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm
> > *pll_28nm, struct clk_hw **prov> 
> >   	if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> >   	
> >   		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> > 
> > +	else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226)
> > +		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226;
> > 
> >   	else
> >   	
> >   		vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
> > 
> > @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
> > 
> >   	.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
> >   
> >   };
> > 
> > +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = {
> > +	.has_phy_regulator = true,
> > +	.regulator_data = dsi_phy_28nm_regulators,
> > +	.num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators),
> > +	.ops = {
> > +		.enable = dsi_28nm_phy_enable,
> > +		.disable = dsi_28nm_phy_disable,
> > +		.pll_init = dsi_pll_28nm_init,
> > +		.save_pll_state = dsi_28nm_pll_save_state,
> > +		.restore_pll_state = dsi_28nm_pll_restore_state,
> > +	},
> > +	.min_pll_rate = VCO_MIN_RATE,
> > +	.max_pll_rate = VCO_MAX_RATE,
> > +	.io_start = { 0xfd922b00 },
> > +	.num_dsi_phy = 1,
> > +	.quirks = DSI_PHY_28NM_QUIRK_PHY_8226,
> > +};
Bjorn Andersson July 10, 2023, 5:07 a.m. UTC | #7 
On Thu, 01 Jun 2023 19:00:07 +0200, Luca Weiss wrote:
> This series adds the required configs for MDP5 and DSI blocks that are
> needed for MDSS on MSM8226. Finally we can add the new nodes into the
> dts.
> 
> Tested on apq8026-lg-lenok and msm8926-htc-memul.
> 
> 
> [...]

Applied, thanks!

[7/7] ARM: dts: qcom: msm8226: Add mdss nodes
      commit: d5fb01ad5eb449ccfd950e946a882639cad168b3

Best regards,