| Message ID | b834b2f5-e505-71be-c694-bbf529ec6bd4@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. | expand |
On 6/15/23 09:06, Robin Dapp wrote: > Hi, > > Changes from v1: > - Revamped the target selectors again. > - Fixed some syntax as well as caching errors that were still present. > - Adjusted some test cases I missed. > > The current situation with target selectors is improvable at best. > We definitely need to discern between being able to build a > test with the current configuration and running the test on the > current target which this patch attempts to do. There might > be a need for more fine-grained checks in the future that could > also go into our target-specific riscv.exp in the subdirectories > but for now I think we're good. > > A bit more detail is in the patch description below. The testsuite > is as clean as before for the configurations I tried: default, rv64gcv, > rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't > overlook tests that appear unsupported now but shouldn't be. > > @Pan: No need to check the old version anymore, thanks. This patch > is preferred. > > Regards > Robin > > > This introduces new checks for run tests. Currently we have > riscv_vector as well as rv32 and rv64 which all check if GCC (with the > current configuration) can build the respective tests. > > Many tests specify e.g. a different -march for vector which > makes the check fail even though we could build as well as run > those tests. > > vector_hw now tries to compile, link and execute a simple vector example > file. If this succeeds the respective test can run. > > Similarly we introduce a zvfh_hw check which will be used in the > upcoming floating-point unop/binop tests as well as rv32_hw and > rv64_hw checks that are currently unused. > > To conclude: > - If we want a testcase to only compile when the current configuration > has vector support we use {riscv_vector}. > - If we want a testcase to run when the current target can supports > executing vector instructions we use {riscv_vector_hw}. > It still needs to be ensured that we can actually build the test > which can be achieved by either > (1) compiling with e.g. -march=rv64gcv or > (2) only enabling the test when the current configuration supports > vector via {riscsv_vector}. > > The same principle applies for zfh, zfhmin and zvfh but we do not yet > have all target selectors. In the meanwhile we need to make sure to > specify the proper -march flags like in (1). > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use > riscv_vector_hw. > * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: > Dito. > * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use. > * g++.target/riscv/rvv/base/bug-10.C: Use. > * g++.target/riscv/rvv/base/bug-11.C: Use. > * g++.target/riscv/rvv/base/bug-12.C: Use. > * g++.target/riscv/rvv/base/bug-13.C: Use. > * g++.target/riscv/rvv/base/bug-14.C: Use. > * g++.target/riscv/rvv/base/bug-15.C: Use. > * g++.target/riscv/rvv/base/bug-16.C: Use. > * g++.target/riscv/rvv/base/bug-17.C: Use. > * g++.target/riscv/rvv/base/bug-2.C: Use. > * g++.target/riscv/rvv/base/bug-23.C: Use. > * g++.target/riscv/rvv/base/bug-3.C: Use. > * g++.target/riscv/rvv/base/bug-4.C: Use. > * g++.target/riscv/rvv/base/bug-5.C: Use. > * g++.target/riscv/rvv/base/bug-6.C: Use. > * g++.target/riscv/rvv/base/bug-7.C: Use. > * g++.target/riscv/rvv/base/bug-8.C: Use. > * g++.target/riscv/rvv/base/bug-9.C: Use. > * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw > and zfh_hw, zfhmin_hw, zvfh_hw checks. I'm OK with the basic idea here and the dejagnu bits look reasonable. So I think the only question is whether or not others agree with the basic direction on the testsuite. So let's give the other RISC-V contributors a couple days to chime in. Jeff
LGTM, I just found this patch still on the list, I mostly tested with qemu, so I don't think that is a problem before, but I realize it's a problem when we run on a real board that does not support those extensions. On Sun, Jun 18, 2023 at 6:07 AM Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > > On 6/15/23 09:06, Robin Dapp wrote: > > Hi, > > > > Changes from v1: > > - Revamped the target selectors again. > > - Fixed some syntax as well as caching errors that were still present. > > - Adjusted some test cases I missed. > > > > The current situation with target selectors is improvable at best. > > We definitely need to discern between being able to build a > > test with the current configuration and running the test on the > > current target which this patch attempts to do. There might > > be a need for more fine-grained checks in the future that could > > also go into our target-specific riscv.exp in the subdirectories > > but for now I think we're good. > > > > A bit more detail is in the patch description below. The testsuite > > is as clean as before for the configurations I tried: default, rv64gcv, > > rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't > > overlook tests that appear unsupported now but shouldn't be. > > > > @Pan: No need to check the old version anymore, thanks. This patch > > is preferred. > > > > Regards > > Robin > > > > > > This introduces new checks for run tests. Currently we have > > riscv_vector as well as rv32 and rv64 which all check if GCC (with the > > current configuration) can build the respective tests. > > > > Many tests specify e.g. a different -march for vector which > > makes the check fail even though we could build as well as run > > those tests. > > > > vector_hw now tries to compile, link and execute a simple vector example > > file. If this succeeds the respective test can run. > > > > Similarly we introduce a zvfh_hw check which will be used in the > > upcoming floating-point unop/binop tests as well as rv32_hw and > > rv64_hw checks that are currently unused. > > > > To conclude: > > - If we want a testcase to only compile when the current configuration > > has vector support we use {riscv_vector}. > > - If we want a testcase to run when the current target can supports > > executing vector instructions we use {riscv_vector_hw}. > > It still needs to be ensured that we can actually build the test > > which can be achieved by either > > (1) compiling with e.g. -march=rv64gcv or > > (2) only enabling the test when the current configuration supports > > vector via {riscsv_vector}. > > > > The same principle applies for zfh, zfhmin and zvfh but we do not yet > > have all target selectors. In the meanwhile we need to make sure to > > specify the proper -march flags like in (1). > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use > > riscv_vector_hw. > > * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use. > > * g++.target/riscv/rvv/base/bug-10.C: Use. > > * g++.target/riscv/rvv/base/bug-11.C: Use. > > * g++.target/riscv/rvv/base/bug-12.C: Use. > > * g++.target/riscv/rvv/base/bug-13.C: Use. > > * g++.target/riscv/rvv/base/bug-14.C: Use. > > * g++.target/riscv/rvv/base/bug-15.C: Use. > > * g++.target/riscv/rvv/base/bug-16.C: Use. > > * g++.target/riscv/rvv/base/bug-17.C: Use. > > * g++.target/riscv/rvv/base/bug-2.C: Use. > > * g++.target/riscv/rvv/base/bug-23.C: Use. > > * g++.target/riscv/rvv/base/bug-3.C: Use. > > * g++.target/riscv/rvv/base/bug-4.C: Use. > > * g++.target/riscv/rvv/base/bug-5.C: Use. > > * g++.target/riscv/rvv/base/bug-6.C: Use. > > * g++.target/riscv/rvv/base/bug-7.C: Use. > > * g++.target/riscv/rvv/base/bug-8.C: Use. > > * g++.target/riscv/rvv/base/bug-9.C: Use. > > * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw > > and zfh_hw, zfhmin_hw, zvfh_hw checks. > I'm OK with the basic idea here and the dejagnu bits look reasonable. > So I think the only question is whether or not others agree with the > basic direction on the testsuite. > > So let's give the other RISC-V contributors a couple days to chime in. > > Jeff
> LGTM, I just found this patch still on the list, I mostly tested with > qemu, so I don't think that is a problem before, but I realize it's a > problem when we run on a real board that does not support those > extensions. I think we can skip this one as I needed to introduce vector_hw and zvfh_hw with another patch anyway. What I still intended to do is an -march-ext=... switch but that might be superseded already by Jörn's patch that I wanted to have a look at soon anyway. Regards Robin
On 7/27/23 06:02, Robin Dapp wrote: >> LGTM, I just found this patch still on the list, I mostly tested with >> qemu, so I don't think that is a problem before, but I realize it's a >> problem when we run on a real board that does not support those >> extensions. > > I think we can skip this one as I needed to introduce vector_hw and > zvfh_hw with another patch anyway. What I still intended to do is an > -march-ext=... switch but that might be superseded already by Jörn's patch > that I wanted to have a look at soon anyway. I'll drop it from patchwork then. jeff
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C index 503b6c37d5f..af4bf7971a0 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C index 151d7364aa0..9d4c467610e 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C index ea992327202..501a4fe6f8b 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C index 2a31e3d6d09..623b0ab93c2 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C index d833d4d80c5..e831b2e82ad 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ +/* { dg-do run { target { riscv_vector && { riscv_vector_hw && rv64 } } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C index 627aa9290f9..73b6a574a32 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C index d90d2d4dc01..6b8fc592837 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C index c29d6379ab5..d04cf4c56f5 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C index 48529c346a3..819fa696c7a 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C index d750a77bd77..93131a5c62b 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C index 1c7e0181f4a..83f86260d6c 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C index 400aea4e0b0..ec0b9a519a7 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C index caa826a5587..867e08bda20 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C index ec6e2903884..1856dc93339 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C index a3ab39750d1..b3a9ff956f4 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C index 97459c6b666..ed9aad01464 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector && riscv_vector_hw } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C index 119ec0ed28e..d37d0c7fd1c 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ +/* { dg-do run { target { rv64 && { riscv_vector && riscv_vector_hw } } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c index d7052b2270c..56361f6c2c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c index a8ecf9767e5..e4eb57ac99a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c index 4f6c8e773c3..65f61b0e932 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c index 3fa6cf35e18..0854561ab6f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c index c4fd81f4bf2..810757a8834 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c index 668f848694b..d889f28b298 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c index 63c05a119a9..a5887e6097f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c index c560af9b85d..22a2c1a18bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c index f6b3770dcbb..30ba27a7b2a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c index 58b69ec393e..a797862366b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index fb6df757c90..a27b9de8862 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c index 7239733d12c..ffbad73c74f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c index a84d22d2a73..e0786abce65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c index 56fd39f4691..e3e4707c987 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c index e50d561bd98..50e6eb23278 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c index 6c45c274c33..2492312554d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c index 05f8d911ad7..6865076ac87 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c index f55d2dfce7f..1b9311c15fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c index d5f0190957a..1bcd50196ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c index 9d1c259f592..85373ced39c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c index d3e187eae68..7520bc483e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c index 5166c9e35a0..8531849b9c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c index b786738ce99..44840042950 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c index 7751384183e..720c0f562ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c index 4af2f18de8a..440d76403ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */ #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c index 16f078a0433..5a2569a4123 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c index 41f688f628c..27a984513fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c index 30996cb2c6e..86247e5b53c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c index 3d43ef0890c..8fa7aa335e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c index 814308bd7af..61a3cc9af03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c index e317eeac2f2..74b0df31ac4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c index a8e4781988e..f5afd17c184 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c index 09a20809c65..d50558b4751 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */ #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c index 1f69b694818..976de18cff4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c index 103b98acdf0..98433e06abd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c index eac5408ce6f..1ad4492453e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c index c6f1fe591f3..79ba4dd3f60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c index 81af4b672a5..8f82f86760e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c index b5e579ef55a..4b7c6b93ce4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c index d864b54229b..d93a7c768d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c index abeb50f21ea..98c7f30ec56 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c index 2870b21a218..a7f44db41ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c index f7c2fdd040d..d6752e99310 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c index 5564dd4a05a..078fe813f08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c index fec5adc56de..f993125d5ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c index 7eb129cde68..a195df342af 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c index e3b97be385b..efa6541d306 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c index 7449f63583c..fd9da162dae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c index 248a30433a5..ba10e22a0d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c index a587dd45eb1..46ea8b0bbb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c index 18dedb0f77d..0728ba60b34 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c index 61dbd5b4f2b..ab02263dd71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c index da7c462e0c3..203bf20e7d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c index 7aaa6b37d52..c8833658ad7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */ #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c index cb216a9543c..78a8f5fd959 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c index 1b51b315ad1..27a4aa01d0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c index 4cae7f4f1a5..46aa2006163 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c index e60b19fab68..19dfddd1ecd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c index b61990915b0..bb8bceffe85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c index b23df90f0ac..e5444253ffb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c index d935d36bf69..7b8c6824621 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */ #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c index 85ec963c47b..a3d0df579d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c index cb054b6c43c..e786bd533e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c index 2cbe1c2bf95..ba0b7609caf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c index 9efb6b2bc39..93e7d40b8af 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c index efd7d293c0b..a2d1fd99359 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c index 53836956c3b..d50c21b1f3c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c index faa6c907337..9c7a3f64bca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c index 6cdeb571711..fcca23e8115 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c index 84baa515610..fa09d38dafc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c index beb0cc2b58b..86185d57908 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c index a14539f72ae..55157b1cce1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c index ca16585a945..5ed28101d66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c index 5b69c2ab0c6..5757255f0ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c index 4abddd5d718..56d744152f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c index f4840d30dc2..5d85aea9d85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c index 2caa09a2c5a..f323897a05a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_vector_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 184fafb020f..98a283ff997 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1804,9 +1804,35 @@ proc check_effective_target_riscv_vector { } { }] } +# Return 1 if the target can execute RISC-V vector instructions, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_vector_hw { } { + + return [check_runtime riscv_vector_hw32 { + int main (void) + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); + asm ("vadd.vv v8,v8,v16" : : : "v8"); + return 0; + } + } "-march=rv32gcv -mabi=ilp32d"] || [check_runtime riscv_vector_hw64 { + int main (void) + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); + asm ("vadd.vv v8,v8,v16" : : : "v8"); + return 0; + } + } "-march=rv64gcv -mabi=lp64d"] +} + # Return 1 if the target is RV32, 0 otherwise. Cache the result. proc check_effective_target_rv32 { } { + if ![istarget riscv32*-*-*] { + return 0 + } + # Check that we are compiling for RV32 by checking the xlen size. return [check_no_compiler_messages riscv_rv32 assembly { #if !defined(__riscv_xlen) @@ -1819,9 +1845,26 @@ proc check_effective_target_rv32 { } { }] } +# Return 1 if the target can execute RV32 executables, 0 otherwise. +# Cache the result. + +proc check_effective_target_rv32_hw { } { + return [check_runtime riscv_rv32_hw { + int main (void) + { + asm ("add t0,t1,t2"); + return 0; + } + } "-march=rv32gc -mabi=ilp32d"] +} + # Return 1 if the target is RV64, 0 otherwise. Cache the result. proc check_effective_target_rv64 { } { + if ![istarget riscv64*-*-*] { + return 0 + } + # Check that we are compiling for RV64 by checking the xlen size. return [check_no_compiler_messages riscv_rv64 assembly { #if !defined(__riscv_xlen) @@ -1834,6 +1877,91 @@ proc check_effective_target_rv64 { } { }] } +# Return 1 if the target can execute RV64 executables, 0 otherwise. +# Cache the result. + +proc check_effective_target_rv64_hw { } { + return [check_runtime riscv_rv64_hw { + int main (void) + { + asm ("addiw t1,t2,4095"); + return 0; + } + } "-march=rv64gc -mabi=lp64d"] +} + +# Return 1 if the target can build and execute Zfh executables, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zfh_hw { } { + if ![check_effective_target_riscv_zfhmin_hw] then { + return 0 + } + + return [check_runtime riscv_riscv_zfh_hw32 { + int main (void) + { + asm ("flh ft0,0(sp)" : : : "ft0"); + asm ("fadd.h ft0,ft0,ft0" : : : "ft0"); + return 0; + } + } "-march=rv32gc_zfh -mabi=ilp32d"] + || [check_runtime riscv_riscv_zfh_hw64 { + int main (void) + { + asm ("flh ft0,0(sp)" : : : "ft0"); + asm ("fadd.h ft0,ft0,ft0" : : : "ft0"); + return 0; + } + } "-march=rv64gc_zfh -mabi=lp64d"] +} + +# Return 1 if the target can build and execute Zfhmin executables, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zfhmin_hw { } { + return [check_runtime riscv_riscv_zfhmin_hw32 { + int main (void) + { + asm ("flh ft0,0(sp)" : : : "ft0"); + return 0; + } + } "-march=rv32gc_zfhmin -mabi=ilp32d"] + || [check_runtime riscv_riscv_zfhmin_hw64 { + int main (void) + { + asm ("flh ft0,0(sp)" : : : "ft0"); + return 0; + } + } "-march=rv64gc_zfhmin -mabi=lp64d"] +} + +# Return 1 if the target can build and execute Zvfh executables, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zvfh_hw { } { + if ![check_effective_target_riscv_vector_hw] then { + return 0 + } + + return [check_runtime riscv_zvfh_hw32 { + int main (void) + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); + asm ("vfadd.vv v8,v8,v16" : : : "v8"); + return 0; + } + } "-march=rv32gcv_zvfh -mabi=ilp32d"] + || [check_runtime riscv_zvfh_hw64 { + int main (void) + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); + asm ("vfadd.vv v8,v8,v16" : : : "v8"); + return 0; + } + } "-march=rv64gcv_zvfh -mabi=lp64d"] +} + # Return 1 if the target OS supports running SSE executables, 0 # otherwise. Cache the result.
Hi, Changes from v1: - Revamped the target selectors again. - Fixed some syntax as well as caching errors that were still present. - Adjusted some test cases I missed. The current situation with target selectors is improvable at best. We definitely need to discern between being able to build a test with the current configuration and running the test on the current target which this patch attempts to do. There might be a need for more fine-grained checks in the future that could also go into our target-specific riscv.exp in the subdirectories but for now I think we're good. A bit more detail is in the patch description below. The testsuite is as clean as before for the configurations I tried: default, rv64gcv, rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't overlook tests that appear unsupported now but shouldn't be. @Pan: No need to check the old version anymore, thanks. This patch is preferred. Regards Robin This introduces new checks for run tests. Currently we have riscv_vector as well as rv32 and rv64 which all check if GCC (with the current configuration) can build the respective tests. Many tests specify e.g. a different -march for vector which makes the check fail even though we could build as well as run those tests. vector_hw now tries to compile, link and execute a simple vector example file. If this succeeds the respective test can run. Similarly we introduce a zvfh_hw check which will be used in the upcoming floating-point unop/binop tests as well as rv32_hw and rv64_hw checks that are currently unused. To conclude: - If we want a testcase to only compile when the current configuration has vector support we use {riscv_vector}. - If we want a testcase to run when the current target can supports executing vector instructions we use {riscv_vector_hw}. It still needs to be ensured that we can actually build the test which can be achieved by either (1) compiling with e.g. -march=rv64gcv or (2) only enabling the test when the current configuration supports vector via {riscsv_vector}. The same principle applies for zfh, zfhmin and zvfh but we do not yet have all target selectors. In the meanwhile we need to make sure to specify the proper -march flags like in (1). gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use riscv_vector_hw. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Dito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito. * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito. * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito. * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito. * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito. * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito. * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito. * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use. * g++.target/riscv/rvv/base/bug-10.C: Use. * g++.target/riscv/rvv/base/bug-11.C: Use. * g++.target/riscv/rvv/base/bug-12.C: Use. * g++.target/riscv/rvv/base/bug-13.C: Use. * g++.target/riscv/rvv/base/bug-14.C: Use. * g++.target/riscv/rvv/base/bug-15.C: Use. * g++.target/riscv/rvv/base/bug-16.C: Use. * g++.target/riscv/rvv/base/bug-17.C: Use. * g++.target/riscv/rvv/base/bug-2.C: Use. * g++.target/riscv/rvv/base/bug-23.C: Use. * g++.target/riscv/rvv/base/bug-3.C: Use. * g++.target/riscv/rvv/base/bug-4.C: Use. * g++.target/riscv/rvv/base/bug-5.C: Use. * g++.target/riscv/rvv/base/bug-6.C: Use. * g++.target/riscv/rvv/base/bug-7.C: Use. * g++.target/riscv/rvv/base/bug-8.C: Use. * g++.target/riscv/rvv/base/bug-9.C: Use. * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw and zfh_hw, zfhmin_hw, zvfh_hw checks. --- .../g++.target/riscv/rvv/base/bug-10.C | 2 +- .../g++.target/riscv/rvv/base/bug-11.C | 2 +- .../g++.target/riscv/rvv/base/bug-12.C | 2 +- .../g++.target/riscv/rvv/base/bug-13.C | 2 +- .../g++.target/riscv/rvv/base/bug-14.C | 2 +- .../g++.target/riscv/rvv/base/bug-15.C | 2 +- .../g++.target/riscv/rvv/base/bug-16.C | 2 +- .../g++.target/riscv/rvv/base/bug-17.C | 2 +- .../g++.target/riscv/rvv/base/bug-2.C | 2 +- .../g++.target/riscv/rvv/base/bug-23.C | 2 +- .../g++.target/riscv/rvv/base/bug-3.C | 2 +- .../g++.target/riscv/rvv/base/bug-4.C | 2 +- .../g++.target/riscv/rvv/base/bug-5.C | 2 +- .../g++.target/riscv/rvv/base/bug-6.C | 2 +- .../g++.target/riscv/rvv/base/bug-7.C | 2 +- .../g++.target/riscv/rvv/base/bug-8.C | 2 +- .../g++.target/riscv/rvv/base/bug-9.C | 2 +- .../riscv/rvv/autovec/binop/shift-run.c | 2 +- .../rvv/autovec/binop/shift-scalar-run.c | 2 +- .../riscv/rvv/autovec/binop/vadd-run.c | 2 +- .../riscv/rvv/autovec/binop/vand-run.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-run.c | 2 +- .../riscv/rvv/autovec/binop/vmax-run.c | 2 +- .../riscv/rvv/autovec/binop/vmin-run.c | 2 +- .../riscv/rvv/autovec/binop/vmul-run.c | 2 +- .../riscv/rvv/autovec/binop/vor-run.c | 2 +- .../riscv/rvv/autovec/binop/vrem-run.c | 2 +- .../riscv/rvv/autovec/binop/vsub-run.c | 2 +- .../riscv/rvv/autovec/binop/vxor-run.c | 2 +- .../riscv/rvv/autovec/cmp/vcond_run-1.c | 2 +- .../riscv/rvv/autovec/cmp/vcond_run-2.c | 2 +- .../riscv/rvv/autovec/cmp/vcond_run-3.c | 2 +- .../riscv/rvv/autovec/cmp/vcond_run-4.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-run.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-run.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-run.c | 2 +- .../autovec/partial/multiple_rgroup_run-1.c | 2 +- .../autovec/partial/multiple_rgroup_run-2.c | 2 +- .../autovec/partial/multiple_rgroup_run-3.c | 2 +- .../autovec/partial/multiple_rgroup_run-4.c | 2 +- .../rvv/autovec/partial/single_rgroup_run-1.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-1.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-2.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-3.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-4.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-5.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-6.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-7.c | 2 +- .../riscv/rvv/autovec/series_run-1.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-1.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-2.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-3.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-4.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-5.c | 2 +- .../riscv/rvv/autovec/ternop/ternop_run-6.c | 2 +- .../riscv/rvv/autovec/unop/abs-run.c | 2 +- .../riscv/rvv/autovec/unop/vneg-run.c | 2 +- .../riscv/rvv/autovec/unop/vnot-run.c | 2 +- .../vls-vlmax/init-repeat-sequence-run-1.c | 2 +- .../vls-vlmax/init-repeat-sequence-run-2.c | 2 +- .../vls-vlmax/init-repeat-sequence-run-3.c | 2 +- .../rvv/autovec/vls-vlmax/insert_run-1.c | 2 +- .../rvv/autovec/vls-vlmax/insert_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-1.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-2.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-3.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-4.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-5.c | 2 +- .../rvv/autovec/vls-vlmax/repeat_run-6.c | 2 +- .../riscv/rvv/autovec/vmv-imm-run.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-3.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-4.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-5.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-6.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-7.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-8.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-9.c | 2 +- gcc/testsuite/lib/target-supports.exp | 128 ++++++++++++++++++ 95 files changed, 222 insertions(+), 94 deletions(-)