| Message ID | 20230530161129.313258-2-fbarrat@linux.ibm.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Various xive fixes | expand |
On 5/30/23 18:11, Frederic Barrat wrote: > Add basic read/write support for the TCTXT Config register on P10. qemu > doesn't do anything with it yet, but it avoids logging a guest error > when skiboot configures the fused-core state: > > qemu-system-ppc64 -machine powernv10 ... -d guest_errors > ... > [ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0... > XIVE[0] - TCTXT: invalid read @140 > XIVE[0] - TCTXT: invalid write @140 Reviewed-by: Cédric Le Goater <clg@kaod.org> If you respin, please add the same kind of support to POWER9. Thanks, C. > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- > hw/intc/pnv_xive2.c | 8 +++++++- > hw/intc/pnv_xive2_regs.h | 4 ++++ > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 7176d70234..889e409929 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1265,6 +1265,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, > case TCTXT_EN1_RESET: > val = xive->tctxt_regs[TCTXT_EN1 >> 3]; > break; > + case TCTXT_CFG: > + val = xive->tctxt_regs[reg]; > + break; > default: > xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); > } > @@ -1276,6 +1279,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, > uint64_t val, unsigned size) > { > PnvXive2 *xive = PNV_XIVE2(opaque); > + uint32_t reg = offset >> 3; > > switch (offset) { > /* > @@ -1297,7 +1301,9 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, > case TCTXT_EN1_RESET: > xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; > break; > - > + case TCTXT_CFG: > + xive->tctxt_regs[reg] = val; > + break; > default: > xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); > return; > diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h > index 0c096e4adb..8f1e0a1fde 100644 > --- a/hw/intc/pnv_xive2_regs.h > +++ b/hw/intc/pnv_xive2_regs.h > @@ -405,6 +405,10 @@ > #define X_TCTXT_EN1_RESET 0x307 > #define TCTXT_EN1_RESET 0x038 > > +/* TCTXT Config register */ > +#define X_TCTXT_CFG 0x328 > +#define TCTXT_CFG 0x140 > + > /* > * VSD Tables > */
On 30/05/2023 18:31, Cédric Le Goater wrote: > On 5/30/23 18:11, Frederic Barrat wrote: >> Add basic read/write support for the TCTXT Config register on P10. qemu >> doesn't do anything with it yet, but it avoids logging a guest error >> when skiboot configures the fused-core state: >> >> qemu-system-ppc64 -machine powernv10 ... -d guest_errors >> ... >> [ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0... >> XIVE[0] - TCTXT: invalid read @140 >> XIVE[0] - TCTXT: invalid write @140 > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > > If you respin, please add the same kind of support to POWER9. It's already in place for read and write: static void pnv_xive_ic_reg_write() ... case PC_TCTXT_CFG: Skiboot is using it and we don't get an error message, even with guest_errors. So it looks good. Fred > > Thanks, > > C. > > >> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> >> --- >> hw/intc/pnv_xive2.c | 8 +++++++- >> hw/intc/pnv_xive2_regs.h | 4 ++++ >> 2 files changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c >> index 7176d70234..889e409929 100644 >> --- a/hw/intc/pnv_xive2.c >> +++ b/hw/intc/pnv_xive2.c >> @@ -1265,6 +1265,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void >> *opaque, hwaddr offset, >> case TCTXT_EN1_RESET: >> val = xive->tctxt_regs[TCTXT_EN1 >> 3]; >> break; >> + case TCTXT_CFG: >> + val = xive->tctxt_regs[reg]; >> + break; >> default: >> xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); >> } >> @@ -1276,6 +1279,7 @@ static void pnv_xive2_ic_tctxt_write(void >> *opaque, hwaddr offset, >> uint64_t val, unsigned size) >> { >> PnvXive2 *xive = PNV_XIVE2(opaque); >> + uint32_t reg = offset >> 3; >> switch (offset) { >> /* >> @@ -1297,7 +1301,9 @@ static void pnv_xive2_ic_tctxt_write(void >> *opaque, hwaddr offset, >> case TCTXT_EN1_RESET: >> xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; >> break; >> - >> + case TCTXT_CFG: >> + xive->tctxt_regs[reg] = val; >> + break; >> default: >> xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, >> offset); >> return; >> diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h >> index 0c096e4adb..8f1e0a1fde 100644 >> --- a/hw/intc/pnv_xive2_regs.h >> +++ b/hw/intc/pnv_xive2_regs.h >> @@ -405,6 +405,10 @@ >> #define X_TCTXT_EN1_RESET 0x307 >> #define TCTXT_EN1_RESET 0x038 >> +/* TCTXT Config register */ >> +#define X_TCTXT_CFG 0x328 >> +#define TCTXT_CFG 0x140 >> + >> /* >> * VSD Tables >> */ >
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 7176d70234..889e409929 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1265,6 +1265,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, case TCTXT_EN1_RESET: val = xive->tctxt_regs[TCTXT_EN1 >> 3]; break; + case TCTXT_CFG: + val = xive->tctxt_regs[reg]; + break; default: xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); } @@ -1276,6 +1279,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { PnvXive2 *xive = PNV_XIVE2(opaque); + uint32_t reg = offset >> 3; switch (offset) { /* @@ -1297,7 +1301,9 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, case TCTXT_EN1_RESET: xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; break; - + case TCTXT_CFG: + xive->tctxt_regs[reg] = val; + break; default: xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); return; diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index 0c096e4adb..8f1e0a1fde 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -405,6 +405,10 @@ #define X_TCTXT_EN1_RESET 0x307 #define TCTXT_EN1_RESET 0x038 +/* TCTXT Config register */ +#define X_TCTXT_CFG 0x328 +#define TCTXT_CFG 0x140 + /* * VSD Tables */
Add basic read/write support for the TCTXT Config register on P10. qemu doesn't do anything with it yet, but it avoids logging a guest error when skiboot configures the fused-core state: qemu-system-ppc64 -machine powernv10 ... -d guest_errors ... [ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0... XIVE[0] - TCTXT: invalid read @140 XIVE[0] - TCTXT: invalid write @140 Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/intc/pnv_xive2.c | 8 +++++++- hw/intc/pnv_xive2_regs.h | 4 ++++ 2 files changed, 11 insertions(+), 1 deletion(-)