diff mbox series

sbsa-ref: switch default cpu core to Neoverse-N1

Message ID 20230506183417.1360427-1-marcin.juszkiewicz@linaro.org
State New
Headers show
Series sbsa-ref: switch default cpu core to Neoverse-N1 | expand

Commit Message

Marcin Juszkiewicz May 6, 2023, 6:34 p.m. UTC
The world outside moves to newer and newer cpu cores. Let move SBSA
Reference Platform to something newer as well.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 hw/arm/sbsa-ref.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Peter Maydell May 12, 2023, 2:50 p.m. UTC | #1
On Sat, 6 May 2023 at 19:34, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> The world outside moves to newer and newer cpu cores. Let move SBSA
> Reference Platform to something newer as well.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
>  hw/arm/sbsa-ref.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 0b93558dde..a1562f944a 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -852,7 +852,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
>
>      mc->init = sbsa_ref_init;
>      mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
> -    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
> +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
>      mc->max_cpus = 512;
>      mc->pci_allow_0_address = true;
>      mc->minimum_page_bits = 12;

Seems reasonable; Leif, any objection?

thanks
-- PMM
Leif Lindholm May 12, 2023, 4:02 p.m. UTC | #2
On 2023-05-12 15:50, Peter Maydell wrote:
> On Sat, 6 May 2023 at 19:34, Marcin Juszkiewicz
> <marcin.juszkiewicz@linaro.org> wrote:
>>
>> The world outside moves to newer and newer cpu cores. Let move SBSA
>> Reference Platform to something newer as well.
>>
>> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>> ---
>>   hw/arm/sbsa-ref.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
>> index 0b93558dde..a1562f944a 100644
>> --- a/hw/arm/sbsa-ref.c
>> +++ b/hw/arm/sbsa-ref.c
>> @@ -852,7 +852,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
>>
>>       mc->init = sbsa_ref_init;
>>       mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
>> -    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
>> +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
>>       mc->max_cpus = 512;
>>       mc->pci_allow_0_address = true;
>>       mc->minimum_page_bits = 12;
> 
> Seems reasonable; Leif, any objection?

None.

Longer-term, I still want to move to "max" as the default, but that is 
likely to require some invasive changes to TF-A, and this is already a 
huge improvement. So:
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

Thanks!

/
     Leif
Marcin Juszkiewicz May 12, 2023, 4:11 p.m. UTC | #3
W dniu 12.05.2023 o 18:02, Leif Lindholm pisze:
> Longer-term, I still want to move to "max" as the default, but that is 
> likely to require some invasive changes to TF-A, and this is already a 
> huge improvement.

Firmware was main reason why I not moved to "max". It is easier to keep 
system running when it models already existing core.

For me "max" stopped booting when FEAT_FGT landed in QEMU. Took over 3 
months to enable it in TF-A.
Peter Maydell May 15, 2023, 3:28 p.m. UTC | #4
On Fri, 12 May 2023 at 17:02, Leif Lindholm <quic_llindhol@quicinc.com> wrote:
>
> On 2023-05-12 15:50, Peter Maydell wrote:
> > On Sat, 6 May 2023 at 19:34, Marcin Juszkiewicz
> > <marcin.juszkiewicz@linaro.org> wrote:
> >>
> >> The world outside moves to newer and newer cpu cores. Let move SBSA
> >> Reference Platform to something newer as well.
> >>
> >> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> >> ---
> >>   hw/arm/sbsa-ref.c | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> >> index 0b93558dde..a1562f944a 100644
> >> --- a/hw/arm/sbsa-ref.c
> >> +++ b/hw/arm/sbsa-ref.c
> >> @@ -852,7 +852,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
> >>
> >>       mc->init = sbsa_ref_init;
> >>       mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
> >> -    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
> >> +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
> >>       mc->max_cpus = 512;
> >>       mc->pci_allow_0_address = true;
> >>       mc->minimum_page_bits = 12;
> >
> > Seems reasonable; Leif, any objection?
>
> None.
>
> Longer-term, I still want to move to "max" as the default, but that is
> likely to require some invasive changes to TF-A, and this is already a
> huge improvement. So:
> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

Thanks; applied to target-arm.next.

-- PMM
diff mbox series

Patch

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 0b93558dde..a1562f944a 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -852,7 +852,7 @@  static void sbsa_ref_class_init(ObjectClass *oc, void *data)
 
     mc->init = sbsa_ref_init;
     mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
-    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
     mc->max_cpus = 512;
     mc->pci_allow_0_address = true;
     mc->minimum_page_bits = 12;