| Message ID | 20230412073830.13928-17-matt@traverse.com.au |
|---|---|
| State | Accepted |
| Commit | 51b9254e02dfd37c98592ad4ffc6e4b4c5a06db7 |
| Delegated to: | Peng Fan |
| Headers | show |
| Series | Synchronise LS1088A/Ten64 device tree with Linux | expand |
On 4/12/2023 3:38 PM, Mathew McBride wrote: > This is effectively: > > cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ > u-boot/arch/arm/dts/fsl-ls1088a.dtsi > > Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. > > Signed-off-by: Mathew McBride<matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com>
On 4/12/2023 3:38 PM, Mathew McBride wrote: > This is effectively: > > cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ > u-boot/arch/arm/dts/fsl-ls1088a.dtsi > > Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. > > Signed-off-by: Mathew McBride <matt@traverse.com.au> > --- > arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- > 1 file changed, 304 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi > index d5822520fb..e5fb137ac0 100644 > --- a/arch/arm/dts/fsl-ls1088a.dtsi > +++ b/arch/arm/dts/fsl-ls1088a.dtsi > @@ -1,18 +1,27 @@ > -// SPDX-License-Identifier: GPL-2.0+ OR X11 > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) I just relized that I overlooked this. Is it fine to update this？ I could drop this line change in my local if need to keep original license. Regards, Peng. > /* > - * NXP ls1088a SOC common device tree source > + * Device Tree Include file for NXP Layerscape-1088A family SoC. > + * > + * Copyright 2017-2020 NXP > + * > + * Harninder Rai <harninder.rai@nxp.com> > * > - * Copyright 2017, 2020-2021, 2023 NXP > */ > - > #include <dt-bindings/clock/fsl,qoriq-clockgen.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/thermal/thermal.h> > + > / { > compatible = "fsl,ls1088a"; > interrupt-parent = <&gic>; > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + crypto = &crypto; > + rtc1 = &ftm_alarm0; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -121,12 +130,73 @@ > }; > }; > > + thermal-zones { > + core-cluster { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 0>; > + > + trips { > + core_cluster_alert: core-cluster-alert { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + core-cluster-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&core_cluster_alert>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + soc { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 1>; > + > + trips { > + soc-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + }; > + > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ > - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ > - <1 11 0x8>, /* Virtual PPI, active-low */ > - <1 10 0x8>; /* Hypervisor PPI, active-low */ > + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ > + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ > + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ > + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > }; > > sysclk: sysclk { > @@ -136,6 +206,13 @@ > clock-output-names = "sysclk"; > }; > > + reboot { > + compatible = "syscon-reboot"; > + regmap = <&reset>; > + offset = <0x0>; > + mask = <0x02>; > + }; > + > soc { > compatible = "simple-bus"; > #address-cells = <2>; > @@ -150,13 +227,105 @@ > clocks = <&sysclk>; > }; > > - duart0: serial@21c0500 { > - compatible = "fsl,ns16550", "ns16550a"; > - reg = <0x0 0x21c0500 0x0 0x100>; > + dcfg: dcfg@1e00000 { > + compatible = "fsl,ls1088a-dcfg", "syscon"; > + reg = <0x0 0x1e00000 0x0 0x10000>; > + little-endian; > + }; > + > + reset: syscon@1e60000 { > + compatible = "fsl,ls1088a-reset", "syscon"; > + reg = <0x0 0x1e60000 0x0 0x10000>; > + }; > + > + isc: syscon@1f70000 { > + compatible = "fsl,ls1088a-isc", "syscon"; > + reg = <0x0 0x1f70000 0x0 0x10000>; > + little-endian; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x1f70000 0x10000>; > + > + extirq: interrupt-controller@14 { > + compatible = "fsl,ls1088a-extirq"; > + #interrupt-cells = <2>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x14 4>; > + interrupt-map = > + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0xf 0x0>; > + }; > + }; > + > + sfp: efuse@1e80000 { > + compatible = "fsl,ls1028a-sfp"; > + reg = <0x0 0x1e80000 0x0 0x10000>; > clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > QORIQ_CLK_PLL_DIV(4)>; > - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; > - status = "disabled"; > + clock-names = "sfp"; > + }; > + > + tmu: tmu@1f80000 { > + compatible = "fsl,qoriq-tmu"; > + reg = <0x0 0x1f80000 0x0 0x10000>; > + interrupts = <0 23 0x4>; > + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; > + fsl,tmu-calibration = > + /* Calibration data group 1 */ > + <0x00000000 0x00000023 > + 0x00000001 0x0000002a > + 0x00000002 0x00000030 > + 0x00000003 0x00000037 > + 0x00000004 0x0000003d > + 0x00000005 0x00000044 > + 0x00000006 0x0000004a > + 0x00000007 0x00000051 > + 0x00000008 0x00000057 > + 0x00000009 0x0000005e > + 0x0000000a 0x00000064 > + 0x0000000b 0x0000006b > + /* Calibration data group 2 */ > + 0x00010000 0x00000022 > + 0x00010001 0x0000002a > + 0x00010002 0x00000032 > + 0x00010003 0x0000003a > + 0x00010004 0x00000042 > + 0x00010005 0x0000004a > + 0x00010006 0x00000052 > + 0x00010007 0x0000005a > + 0x00010008 0x00000062 > + 0x00010009 0x0000006a > + /* Calibration data group 3 */ > + 0x00020000 0x00000021 > + 0x00020001 0x0000002b > + 0x00020002 0x00000035 > + 0x00020003 0x00000040 > + 0x00020004 0x0000004a > + 0x00020005 0x00000054 > + 0x00020006 0x0000005e > + /* Calibration data group 4 */ > + 0x00030000 0x00000010 > + 0x00030001 0x0000001c > + 0x00030002 0x00000027 > + 0x00030003 0x00000032 > + 0x00030004 0x0000003e > + 0x00030005 0x00000049 > + 0x00030006 0x00000054 > + 0x00030007 0x00000060>; > + little-endian; > + #thermal-sensor-cells = <1>; > }; > > dspi: spi@2100000 { > @@ -173,6 +342,15 @@ > status = "disabled"; > }; > > + duart0: serial@21c0500 { > + compatible = "fsl,ns16550", "ns16550a"; > + reg = <0x0 0x21c0500 0x0 0x100>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(4)>; > + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > duart1: serial@21c0600 { > compatible = "fsl,ns16550", "ns16550a"; > reg = <0x0 0x21c0600 0x0 0x100>; > @@ -582,6 +760,20 @@ > <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; > }; > > + console@8340020 { > + compatible = "fsl,dpaa2-console"; > + reg = <0x00000000 0x08340020 0 0x2>; > + }; > + > + ptp-timer@8b95000 { > + compatible = "fsl,dpaa2-ptp"; > + reg = <0x0 0x8b95000 0x0 0x100>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(1)>; > + little-endian; > + fsl,extts-fifo; > + }; > + > emdio1: mdio@8b96000 { > compatible = "fsl,fman-memac-mdio"; > reg = <0x0 0x8b96000 0x0 0x1000>; > @@ -682,6 +874,86 @@ > }; > }; > > + cluster1_core0_watchdog: wdt@c000000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc000000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster1_core1_watchdog: wdt@c010000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc010000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster1_core2_watchdog: wdt@c020000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc020000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster1_core3_watchdog: wdt@c030000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc030000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster2_core0_watchdog: wdt@c100000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc100000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster2_core1_watchdog: wdt@c110000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc110000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster2_core2_watchdog: wdt@c120000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc120000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > + cluster2_core3_watchdog: wdt@c130000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x0 0xc130000 0x0 0x1000>; > + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>, > + <&clockgen QORIQ_CLK_PLATFORM_PLL > + QORIQ_CLK_PLL_DIV(16)>; > + clock-names = "wdog_clk", "apb_pclk"; > + }; > + > fsl_mc: fsl-mc@80c000000 { > compatible = "fsl,qoriq-mc"; > reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ > @@ -754,10 +1026,26 @@ > }; > }; > }; > + > + rcpm: power-controller@1e34040 { > + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; > + reg = <0x0 0x1e34040 0x0 0x18>; > + #fsl,rcpm-wakeup-cells = <6>; > + little-endian; > + }; > + > + ftm_alarm0: timer@2800000 { > + compatible = "fsl,ls1088a-ftm-alarm"; > + reg = <0x0 0x2800000 0x0 0x10000>; > + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > > - psci { > - compatible = "arm,psci-0.2"; > - method = "smc"; > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > }; > };
On Fri, Apr 28, 2023 at 11:33:23AM +0800, Peng Fan wrote: > > > On 4/12/2023 3:38 PM, Mathew McBride wrote: > > This is effectively: > > > > cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ > > u-boot/arch/arm/dts/fsl-ls1088a.dtsi > > > > Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. > > > > Signed-off-by: Mathew McBride <matt@traverse.com.au> > > --- > > arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- > > 1 file changed, 304 insertions(+), 16 deletions(-) > > > > diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi > > index d5822520fb..e5fb137ac0 100644 > > --- a/arch/arm/dts/fsl-ls1088a.dtsi > > +++ b/arch/arm/dts/fsl-ls1088a.dtsi > > @@ -1,18 +1,27 @@ > > -// SPDX-License-Identifier: GPL-2.0+ OR X11 > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > I just relized that I overlooked this. Is it fine to update this？ > > I could drop this line change in my local if need to keep original license. As it's part of the re-sync it's fine.
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d5822520fb..e5fb137ac0 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,18 +1,27 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1088a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1088A family SoC. + * + * Copyright 2017-2020 NXP + * + * Harninder Rai <harninder.rai@nxp.com> * - * Copyright 2017, 2020-2021, 2023 NXP */ - #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> + / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + aliases { + crypto = &crypto; + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -121,12 +130,73 @@ }; }; + thermal-zones { + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ - <1 11 0x8>, /* Virtual PPI, active-low */ - <1 10 0x8>; /* Hypervisor PPI, active-low */ + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; }; sysclk: sysclk { @@ -136,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -150,13 +227,105 @@ clocks = <&sysclk>; }; - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; + dcfg: dcfg@1e00000 { + compatible = "fsl,ls1088a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + + isc: syscon@1f70000 { + compatible = "fsl,ls1088a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xf 0x0>; + }; + }; + + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + clock-names = "sfp"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000030 + 0x00000003 0x00000037 + 0x00000004 0x0000003d + 0x00000005 0x00000044 + 0x00000006 0x0000004a + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005e + 0x0000000a 0x00000064 + 0x0000000b 0x0000006b + /* Calibration data group 2 */ + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a + /* Calibration data group 3 */ + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x00000040 + 0x00020004 0x0000004a + 0x00020005 0x00000054 + 0x00020006 0x0000005e + /* Calibration data group 4 */ + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000027 + 0x00030003 0x00000032 + 0x00030004 0x0000003e + 0x00030005 0x00000049 + 0x00030006 0x00000054 + 0x00030007 0x00000060>; + little-endian; + #thermal-sensor-cells = <1>; }; dspi: spi@2100000 { @@ -173,6 +342,15 @@ status = "disabled"; }; + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; @@ -582,6 +760,20 @@ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; }; + console@8340020 { + compatible = "fsl,dpaa2-console"; + reg = <0x00000000 0x08340020 0 0x2>; + }; + + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + little-endian; + fsl,extts-fifo; + }; + emdio1: mdio@8b96000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8b96000 0x0 0x1000>; @@ -682,6 +874,86 @@ }; }; + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core2_watchdog: wdt@c020000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc020000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core3_watchdog: wdt@c030000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc030000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt@c100000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt@c110000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core2_watchdog: wdt@c120000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc120000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core3_watchdog: wdt@c130000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc130000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ @@ -754,10 +1026,26 @@ }; }; }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; }; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; }; };
This is effectively: cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. Signed-off-by: Mathew McBride <matt@traverse.com.au> --- arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- 1 file changed, 304 insertions(+), 16 deletions(-)