| Message ID | 20230331215804.783439-1-ahalaney@redhat.com |
|---|---|
| Headers | show |
| Series | Add EMAC3 support for sa8540p-ride (devicetree/clk bits) | expand |
On 31/03/2023 23:58, Andrew Halaney wrote: > Enable both the MACs found on the board. > > ethernet0 and ethernet1 both ultimately go to a series of on board > switches which aren't managed by this processor. > > +ðernet0 { > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + > + max-speed = <1000>; > + phy-handle = <&rgmii_phy>; > + phy-mode = "rgmii-txid"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <ðernet0_default>; > + > + status = "okay"; > + > + mdio { > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + > + compatible = "snps,dwmac-mdio"; Compatible is always, always the first property. Best regards, Krzysztof
On 31.03.2023 23:58, Andrew Halaney wrote: > This platform has 2 MACs integrated in it, go ahead and describe them. > > Signed-off-by: Andrew Halaney <ahalaney@redhat.com> > --- > > Changes since v2: > * Fix spacing (Konrad) > > Changes since v1: > * None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 42bfa9fa5b96..f28ea86b128d 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -761,6 +761,65 @@ soc: soc@0 { > ranges = <0 0 0 0 0x10 0>; > dma-ranges = <0 0 0 0 0x10 0>; > > + ethernet0: ethernet@20000 { > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x00020000 0x0 0x10000>, > + <0x0 0x00036000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC0_AXI_CLK>, > + <&gcc GCC_EMAC0_SLV_AHB_CLK>, > + <&gcc GCC_EMAC0_PTP_CLK>, > + <&gcc GCC_EMAC0_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_lpi"; > + iommus = <&apps_smmu 0x4c0 0xf>; > + power-domains = <&gcc EMAC_0_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > + ethernet1: ethernet@23000000 { Nodes under /soc should be ordered by their unit address, so in this case it belongs after dispcc1: clock-controller@.. With that fixed: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x23000000 0x0 0x10000>, > + <0x0 0x23016000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC1_AXI_CLK>, > + <&gcc GCC_EMAC1_SLV_AHB_CLK>, > + <&gcc GCC_EMAC1_PTP_CLK>, > + <&gcc GCC_EMAC1_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_lpi"; > + > + iommus = <&apps_smmu 0x40 0xf>; > + power-domains = <&gcc EMAC_1_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > gcc: clock-controller@100000 { > compatible = "qcom,gcc-sc8280xp"; > reg = <0x0 0x00100000 0x0 0x1f0000>;
This is a forward port / upstream refactor of code delivered downstream by Qualcomm over at [0] to enable the DWMAC5 based implementation called EMAC3 on the sa8540p-ride dev board. From what I can tell with the board schematic in hand, as well as the code delivered, the main changes needed are: 1. A new address space layout for /dwmac5/EMAC3 MTL/DMA regs 2. A new programming sequence required for the EMAC3 base platforms This series addresses the devicetree and clock changes to support this hardware bringup. As requested[1], it has been split up by compile time / maintainer tree. The associated v3 of the netdev specific changes can be found at [2]. Together, they result in the ethernet controller working for both controllers on this platform. [0] https://git.codelinaro.org/clo/la/kernel/ark-5.14/-/commit/510235ad02d7f0df478146fb00d7a4ba74821b17 [1] https://lore.kernel.org/netdev/20230320202802.4e7dc54c@kernel.org/ [2] https://lore.kernel.org/netdev/20230331214549.756660-1-ahalaney@redhat.com/T/#m0afcad0e8031c02bcb5dbfb86cb8acfc287968fe v2: https://lore.kernel.org/netdev/20230320221617.236323-1-ahalaney@redhat.com/ v1: https://lore.kernel.org/netdev/20230313165620.128463-1-ahalaney@redhat.com/ Thanks, Andrew Andrew Halaney (3): clk: qcom: gcc-sc8280xp: Add EMAC GDSCs arm64: dts: qcom: sc8280xp: Add ethernet nodes arm64: dts: qcom: sa8540p-ride: Add ethernet nodes arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 181 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++ drivers/clk/qcom/gcc-sc8280xp.c | 18 ++ include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 2 + 4 files changed, 260 insertions(+)