| Message ID | 20221117105249.115649-1-tudor.ambarus@microchip.com |
|---|---|
| Headers | show |
| Series | spi: Introduce spi-cs-setup-ns dt property | expand |
On Thu, 17 Nov 2022 12:52:41 +0200, Tudor Ambarus wrote: > SPI NOR flashes have specific cs-setup time requirements without which > they can't work at frequencies close to their maximum supported frequency, > as they miss the first bits of the instruction command. Unrecognized > commands are ignored, thus the flash will be unresponsive. Introduce the > spi-cs-setup-ns property to allow spi devices to specify their cs setup > time. > > [...] Applied to broonie/spi.git for-next Thanks! [1/8] spi: dt-bindings: Introduce spi-cs-setup-ns property commit: f6c911f3308c1cfb97ae1da6654080d7104e2df2 [2/8] spi: Introduce spi-cs-setup-ns property commit: 33a2fde5f77bd744b8bd0c694bc173cc968e55a5 [3/8] spi: Reintroduce spi_set_cs_timing() commit: 684a47847ae639689e7b823251975348a8e5434f [4/8] spi: atmel-quadspi: Add support for configuring CS timing commit: f732646d0ccd22f42ed7de5e59c0abb7a848e034 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Hi Tudor, On 17/11/2022 at 11:52, Tudor Ambarus wrote: > sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum > operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated > at 3.3V, increase its maximum supported frequency to 104MHz. The > increasing of the spi-max-frequency value requires the setting of the > "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. > > The sst26vf064b datasheet specifies just a minimum value for the > "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no > maximum time specified. I determined experimentally that 5 ns for the > spi-cs-setup-ns is not enough when the flash is operated close to its > maximum frequency and tests showed that 7 ns is just fine, so set the > spi-cs-setup-ns dt property to 7. > > With the increase of frequency the reads are now faster with ~37%. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > index 83bcf9fe0152..20caf40b4755 100644 > --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { > #size-cells = <1>; > compatible = "jedec,spi-nor"; > reg = <0>; > - spi-max-frequency = <80000000>; > + spi-max-frequency = <104000000>; > + spi-cs-setup-ns = /bits/ 16 <7>; Following the different changes that happened to this property after this post, am I right saying that this must now be changed to: spi-cs-setup-delay-ns = <7>; ? Thanks for your insight. Best regards, Nicolas > spi-rx-bus-width = <4>; > spi-tx-bus-width = <4>; > m25p,fast-read;
On 3/28/23 09:51, Nicolas Ferre wrote: > Hi Tudor, Hi! > > On 17/11/2022 at 11:52, Tudor Ambarus wrote: >> sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum >> operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated >> at 3.3V, increase its maximum supported frequency to 104MHz. The >> increasing of the spi-max-frequency value requires the setting of the >> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. >> >> The sst26vf064b datasheet specifies just a minimum value for the >> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no >> maximum time specified. I determined experimentally that 5 ns for the >> spi-cs-setup-ns is not enough when the flash is operated close to its >> maximum frequency and tests showed that 7 ns is just fine, so set the >> spi-cs-setup-ns dt property to 7. >> >> With the increase of frequency the reads are now faster with ~37%. >> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> >> --- >> arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> index 83bcf9fe0152..20caf40b4755 100644 >> --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { >> #size-cells = <1>; >> compatible = "jedec,spi-nor"; >> reg = <0>; >> - spi-max-frequency = <80000000>; >> + spi-max-frequency = <104000000>; >> + spi-cs-setup-ns = /bits/ 16 <7>; > > Following the different changes that happened to this property after > this post, am I right saying that this must now be changed to: > > spi-cs-setup-delay-ns = <7>; > > ? > Yes, that should do it. I'm amending the series right now. Can you do a little test on your side so that we make sure everything is in place? After the update, something like that should be run on any board (maybe wlsom1-ek?): #!/bin/sh dd if=/dev/urandom of=./qspi_test bs=1M count=6 mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug erase /dev/mtd5 0 6291456 mtd_debug read /dev/mtd5 0 6291456 qspi_read hexdump qspi_read mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug read /dev/mtd5 0 6291456 qspi_read sha1sum qspi_test qspi_read brb, ta
SPI NOR flashes have specific cs-setup time requirements without which they can't work at frequencies close to their maximum supported frequency, as they miss the first bits of the instruction command. Unrecognized commands are ignored, thus the flash will be unresponsive. Introduce the spi-cs-setup-ns property to allow spi devices to specify their cs setup time. Tudor Ambarus (8): spi: dt-bindings: Introduce spi-cs-setup-ns property spi: Introduce spi-cs-setup-ns property spi: Reintroduce spi_set_cs_timing() spi: atmel-quadspi: Add support for configuring CS timing ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency .../bindings/spi/spi-peripheral-props.yaml | 5 +++ arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 +- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 +- arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 +- drivers/spi/atmel-quadspi.c | 34 +++++++++++++++ drivers/spi/spi.c | 43 +++++++++++++++++++ 7 files changed, 90 insertions(+), 4 deletions(-)