| Message ID | 20230217090412.18915-3-chunfeng.yun@mediatek.com |
|---|---|
| State | Accepted |
| Commit | b2eff0340d60d070a8f1c9e58690c8f5714ba9ea |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [v2,1/5] phy: phy-mtk-tphy: remove macros to prepare bitfield value | expand |
On 2/17/23 10:04, Chunfeng Yun wrote: > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > exclude IP0) have a wrong default SOF/ITP interval which is > calculated from the frame counter clock 24Mhz by default, but > in fact, the frame counter clock is 48Mhz, so we shall set the > accurate interval according to 48Mhz for those controllers. > > Note: > The first controller no need set it, but if set it, shall change > tphy's pll at the same time. > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Marek Vasut <marex@denx.de> Feel free to pull the entire series via mediatek tree, so it would go in together.
Hi Marek, On Fri, 2023-02-17 at 14:35 +0100, Marek Vasut wrote: > On 2/17/23 10:04, Chunfeng Yun wrote: > > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > > exclude IP0) have a wrong default SOF/ITP interval which is > > calculated from the frame counter clock 24Mhz by default, but > > in fact, the frame counter clock is 48Mhz, so we shall set the > > accurate interval according to 48Mhz for those controllers. > > > > Note: > > The first controller no need set it, but if set it, shall change > > tphy's pll at the same time. > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > Reviewed-by: Marek Vasut <marex@denx.de> > > Feel free to pull the entire series via mediatek tree, so it would go > in > together. Could you help to apply this series patch, seems no mediatek tree, thanks a lot
On 3/2/23 07:23, Chunfeng Yun (云春峰) wrote: > Hi Marek, Hi, > On Fri, 2023-02-17 at 14:35 +0100, Marek Vasut wrote: >> On 2/17/23 10:04, Chunfeng Yun wrote: >>> There are 4 USB controllers on MT8195, the controllers (IP1~IP3, >>> exclude IP0) have a wrong default SOF/ITP interval which is >>> calculated from the frame counter clock 24Mhz by default, but >>> in fact, the frame counter clock is 48Mhz, so we shall set the >>> accurate interval according to 48Mhz for those controllers. >>> >>> Note: >>> The first controller no need set it, but if set it, shall change >>> tphy's pll at the same time. >>> >>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> >> >> Reviewed-by: Marek Vasut <marex@denx.de> >> >> Feel free to pull the entire series via mediatek tree, so it would go >> in >> together. > Could you help to apply this series patch, seems no mediatek tree, > thanks a lot +CC Tom, it would be good to set up Mediatek tree. Applied to usb/next, thanks.
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 3838a990ec..63dfb793c6 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -14,8 +14,9 @@ #include <power/regulator.h> #include <usb.h> #include <usb/xhci.h> -#include <linux/errno.h> +#include <linux/bitfield.h> #include <linux/compat.h> +#include <linux/errno.h> #include <linux/iopoll.h> /* IPPC (IP Port Control) registers */ @@ -50,6 +51,25 @@ #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08)) #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08)) +/* xHCI CSR */ +#define LS_EOF_CFG 0x930 +#define LSEOF_OFFSET 0x89 + +#define FS_EOF_CFG 0x934 +#define FSEOF_OFFSET 0x2e + +#define SS_GEN1_EOF_CFG 0x93c +#define SSG1EOF_OFFSET 0x78 + +#define HFCNTR_CFG 0x944 +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) + +#define SS_GEN2_EOF_CFG 0x990 +#define SSG2EOF_OFFSET 0x3c + +#define XSEOF_OFFSET_MASK GENMASK(11, 0) + struct mtk_xhci { struct xhci_ctrl ctrl; /* Needs to come first in this struct! */ struct xhci_hccr *hcd; @@ -65,6 +85,30 @@ struct mtk_xhci { u32 u2p_dis_msk; }; +/* + * workaround for mt8195: + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval + * is calculated from the frame counter clock 24M, but in fact, the clock + * is 48M. + */ +static void xhci_mtk_set_frame_interval(struct mtk_xhci *mtk) +{ + void __iomem *mac = (void __iomem *)mtk->hcd; + + if (!ofnode_device_is_compatible(dev_ofnode(mtk->dev), "mediatek,mt8195-xhci")) + return; + + clrsetbits_le32(mac + HFCNTR_CFG, + ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK, + FIELD_PREP(ITP_DELTA_CLK_MASK, 0xa) | + FIELD_PREP(FRMCNT_LEV1_RANG_MASK, 0x12b)); + + clrsetbits_le32(mac + LS_EOF_CFG, XSEOF_OFFSET_MASK, LSEOF_OFFSET); + clrsetbits_le32(mac + FS_EOF_CFG, XSEOF_OFFSET_MASK, FSEOF_OFFSET); + clrsetbits_le32(mac + SS_GEN1_EOF_CFG, XSEOF_OFFSET_MASK, SSG1EOF_OFFSET); + clrsetbits_le32(mac + SS_GEN2_EOF_CFG, XSEOF_OFFSET_MASK, SSG2EOF_OFFSET); +} + static int xhci_mtk_host_enable(struct mtk_xhci *mtk) { int u3_ports_disabed = 0; @@ -278,6 +322,8 @@ static int xhci_mtk_probe(struct udevice *dev) if (ret) goto ssusb_init_err; + xhci_mtk_set_frame_interval(mtk); + mtk->ctrl.quirks = XHCI_MTK_HOST; hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd + HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase))); @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev) static const struct udevice_id xhci_mtk_ids[] = { { .compatible = "mediatek,mtk-xhci" }, + { .compatible = "mediatek,mt8195-xhci" }, { } };
There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we shall set the accurate interval according to 48Mhz for those controllers. Note: The first controller no need set it, but if set it, shall change tphy's pll at the same time. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v2: use FIELD_PREP() suggested by Marek --- drivers/usb/host/xhci-mtk.c | 49 ++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-)