diff mbox series

[v2,7/8] mtd: spi-nor: spansion: Set params->addr_mode_nbytes = 4 for multi-die parts

Message ID 9006f197a4f0f287efaef77a8ff0935d5d7833fb.1675835253.git.Takahiro.Kuwano@infineon.com
State Changes Requested
Delegated to: Ambarus Tudor
Headers show
Series mtd: spi-nor: Add support for Infineon SEMPER s25hl02gt and s25hs02gt | expand

Commit Message

Takahiro Kuwano Feb. 8, 2023, 5:53 a.m. UTC 
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

The params->addr_mode_nbytes is set to 3 during BFPT parse in case of
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4. Infineon SEMPER multi-chip devices are
in 3- or 4-byte address mode by factory default, depending on model number.
3-byte address mode is for backward compatibility for some SoCs. Since we
cannot access to registers in 2nd die by 3-byte addressing. We assume post
BootRom programs change the address mode to 4 before hand-off.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi-nor/spansion.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Tudor Ambarus March 2, 2023, 6:41 a.m. UTC | #1 
On 08.02.2023 07:53, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> The params->addr_mode_nbytes is set to 3 during BFPT parse in case of
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4. Infineon SEMPER multi-chip devices are
> in 3- or 4-byte address mode by factory default, depending on model number.

are the models differentiated by unique IDs?

> 3-byte address mode is for backward compatibility for some SoCs. Since we
> cannot access to registers in 2nd die by 3-byte addressing. We assume post
> BootRom programs change the address mode to 4 before hand-off.

no, we can't make this assumption. The only assumption that we may
accept is that the flash is at the factory default settings. But this is
fragile too, because one can configure the flash in a non volatile way
and change the factory default settings. You can't add support for
flashes that come with 3 byte address mode by default without
discovering the address mode at run-time.

Cheers,
ta
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 45377566ecbd..33b44074f941 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -303,6 +303,18 @@  s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
 	/* Replace Quad Enable with volatile version */
 	nor->params->quad_enable = cypress_nor_quad_enable_volatile;
 
+	/*
+	 * The factory default of address mode in multi-die parts (>128MB) may
+	 * be 3- or 4-byte, depending on model number. Since register address of
+	 * 2nd die is mappeted to 32-bit address space, we cannot access to
+	 * registers in 2nd die in 3-byte mode. 3-byte mode is for backward
+	 * compatibility as some SoCs use 3-byte address in their BootROM. So
+	 * far we assume post BootROM programs change the address mode to 4
+	 * before handing off, rather than calling set_4byte_addr_mode() here.
+	 */
+	if (nor->params->size > SZ_128M)
+		nor->params->addr_mode_nbytes = 4;
+
 	return 0;
 }