Message ID | 20221221034407.19605-1-allen-kh.cheng@mediatek.com |
---|---|
Headers | show |
Series | Add ADSP power domains controller support for MT8192 | expand |
Il 21/12/22 04:44, Allen-KH Cheng ha scritto: > Add buck isolation offset and mask to power domain data. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Il 21/12/22 04:44, Allen-KH Cheng ha scritto: > In MT8192, we need to disable EXT_BUCK_ISO before turning on the ADSP > power pm-domains (mtcmos). > > Add the MTK_SCPD_EXT_BUCK_ISO flag to control the buck isolation > setting in the mediatek power domain driver. > > Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > drivers/soc/mediatek/mtk-pm-domains.c | 8 ++++++++ > drivers/soc/mediatek/mtk-pm-domains.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c > index 09e3c38b8466..63f1e183f645 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.c > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > @@ -218,6 +218,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > if (ret) > goto err_reg; > > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) regmap_[...etc] ...so that we validate that ext_buck_iso_offs is actually present (as I suppose that this is supposed to *never* be 0x0). Regards, Angelo
Il 21/12/22 04:44, Allen-KH Cheng ha scritto: > Add ADSP pm-domains (mtcmos) data for MT8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Il 21/12/22 04:44, Allen-KH Cheng ha scritto: > Add the missing ADSP power domains controller for mt8192-scp_adsp clock > controllers. > > Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 21/12/2022 04:44, Allen-KH Cheng wrote: > Add ADSP pm-domains (mtcmos) data for MT8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h > index b97b2051920f..19e58f0ca1df 100644 > --- a/drivers/soc/mediatek/mt8192-pm-domains.h > +++ b/drivers/soc/mediatek/mt8192-pm-domains.h > @@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > + [MT8192_POWER_DOMAIN_ADSP] = { > + .name = "adsp", > + .sta_mask = BIT(22), > + .ctl_offs = 0x0358, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .ext_buck_iso_offs = 0x039C, Can we get a define for this magic number please? Regards, Matthias > + .ext_buck_iso_mask = BIT(2), > + .bp_infracfg = { > + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP, > + MT8192_TOP_AXI_PROT_EN_2_SET, > + MT8192_TOP_AXI_PROT_EN_2_CLR, > + MT8192_TOP_AXI_PROT_EN_2_STA1), > + }, > + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO, > + }, > [MT8192_POWER_DOMAIN_CAM] = { > .name = "cam", > .sta_mask = BIT(23),