RISC-V: Add vmax*.vv C++ API tests

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmax_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vmax_vv-1.C     | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmax_vv-2.C     | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmax_vv-3.C     | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_mu-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_mu-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_mu-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tu-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tu-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tu-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tum-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tum-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmax_vv_tum-3.C | 160 +++++++++
 .../riscv/rvv/base/vmax_vv_tumu-1.C           | 160 +++++++++
 .../riscv/rvv/base/vmax_vv_tumu-2.C           | 160 +++++++++
 .../riscv/rvv/base/vmax_vv_tumu-3.C           | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv-1.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv-2.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv-3.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tum-1.C           | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tum-2.C           | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tum-3.C           | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tumu-1.C          | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tumu-2.C          | 160 +++++++++
 .../riscv/rvv/base/vmaxu_vv_tumu-3.C          | 160 +++++++++
 30 files changed, 5724 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C

committed, thanks!

On Tue, Jan 31, 2023 at 9:09 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * g++.target/riscv/rvv/base/vmax_vv-1.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv-2.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv-3.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_mu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_mu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_mu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tum-1.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tum-2.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tum-3.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tumu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tumu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmax_vv_tumu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv-1.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv-2.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv-3.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C: New test.
>
> ---
>  .../g++.target/riscv/rvv/base/vmax_vv-1.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv-2.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv-3.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_mu-1.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_mu-2.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_mu-3.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tu-1.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tu-2.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tu-3.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tum-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tum-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmax_vv_tum-3.C | 160 +++++++++
>  .../riscv/rvv/base/vmax_vv_tumu-1.C           | 160 +++++++++
>  .../riscv/rvv/base/vmax_vv_tumu-2.C           | 160 +++++++++
>  .../riscv/rvv/base/vmax_vv_tumu-3.C           | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv-1.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv-2.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv-3.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tum-1.C           | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tum-2.C           | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tum-3.C           | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tumu-1.C          | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tumu-2.C          | 160 +++++++++
>  .../riscv/rvv/base/vmaxu_vv_tumu-3.C          | 160 +++++++++
>  30 files changed, 5724 insertions(+)
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C
>
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C
> new file mode 100644
> index 00000000000..6992c5b5d72
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,vl);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C
> new file mode 100644
> index 00000000000..0721f870732
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,31);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C
> new file mode 100644
> index 00000000000..3e8b594e8bc
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(op1,op2,32);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C
> new file mode 100644
> index 00000000000..5d091a82a80
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C
> new file mode 100644
> index 00000000000..4dccd8ad12c
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C
> new file mode 100644
> index 00000000000..575805c7f4d
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C
> new file mode 100644
> index 00000000000..848964c1502
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C
> new file mode 100644
> index 00000000000..bd82a1e829e
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C
> new file mode 100644
> index 00000000000..29096369280
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C
> new file mode 100644
> index 00000000000..20737dca629
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C
> new file mode 100644
> index 00000000000..157e256814b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C
> new file mode 100644
> index 00000000000..619ee224bbf
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C
> new file mode 100644
> index 00000000000..d0b10f8c756
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C
> new file mode 100644
> index 00000000000..2ea872d5483
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C
> new file mode 100644
> index 00000000000..f13c65279d0
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C
> new file mode 100644
> index 00000000000..bbf361a9212
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vmaxu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C
> new file mode 100644
> index 00000000000..039f4508e12
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vmaxu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C
> new file mode 100644
> index 00000000000..abf8697ea50
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vmaxu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C
> new file mode 100644
> index 00000000000..54701973553
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C
> new file mode 100644
> index 00000000000..052c8d57520
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C
> new file mode 100644
> index 00000000000..d1c3f5c7929
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C
> new file mode 100644
> index 00000000000..c64359da46b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C
> new file mode 100644
> index 00000000000..7a74cf221d7
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C
> new file mode 100644
> index 00000000000..4fd092c2479
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C
> new file mode 100644
> index 00000000000..3f534c63780
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C
> new file mode 100644
> index 00000000000..8ad034ae66b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C
> new file mode 100644
> index 00000000000..c9f4cd08524
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C
> new file mode 100644
> index 00000000000..2b5958ba055
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C
> new file mode 100644
> index 00000000000..8ee92f260e4
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C
> new file mode 100644
> index 00000000000..9474d3b592a
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vmaxu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vmaxu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vmaxu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vmaxu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vmaxu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vmaxu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vmaxu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmaxu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmaxu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> --
> 2.36.3
>