| Message ID | 20230118091829.755-1-allen-kh.cheng@mediatek.com |
|---|---|
| Headers | show |
| Series | Add and update some driver nodes for MT8186 SoC | expand |
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add display nodes and GCE info for MT8186 SoC. Also, add GCE > (Global Command Engine) properties to the display nodes in order to > enable the usage of the CMDQ (Command Queue), which is required for > operating the display. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Can we please add GCE in one commit and the display in another commit? That's just because GCE is not only related to the display nodes, but also to others. Regards, Angelo
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add DPI node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add audio controller node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add ADSP node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index a0b7dacc10cd..2700c830316f 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -640,6 +640,26 @@ > interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; > }; > > + adsp: adsp@10680000 { > + compatible = "mediatek,mt8186-dsp"; > + reg = <0 0x10680000 0 0x2000>, > + <0 0x10800000 0 0x100000>, > + <0 0x1068b000 0 0x100>, > + <0 0x1068f000 0 0x1000>; reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; reaching 82 columns, which is fine. Regards, Angelo
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add MTU3 nodes for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Tested-by: Chen-Yu Tsai <wenst@chromium.org> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75 ++++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index c0a3afd55eaf..3d88480913eb 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -908,6 +908,43 @@ > status = "disabled"; > }; > > + ssusb0: usb@11201000 { > + compatible = "mediatek,mt8186-mtu3", > + "mediatek,mtu3"; 78 columns; compatibles fit in one line. > + reg = <0 0x11201000 0 0x2dff>, > + <0 0x11203e00 0 0x0100>; 80 cols; regs fit in one line. > + reg-names = "mac", "ippc"; > + clocks = <&topckgen CLK_TOP_USB_TOP>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, > + <&infracfg_ao CLK_INFRA_AO_ICUSB>; > + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; > + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; > + phys = <&u2port0 PHY_TYPE_USB2>; > + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + usb_host0: usb@11200000 { > + compatible = "mediatek,mt8186-xhci", > + "mediatek,mtk-xhci"; 90 cols; fits in one line. ...same comments for ssusb1 :-) > + reg = <0 0x11200000 0 0x1000>; > + reg-names = "mac"; > + clocks = <&topckgen CLK_TOP_USB_TOP>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, > + <&infracfg_ao CLK_INFRA_AO_ICUSB>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; > + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; > + interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; > + mediatek,syscon-wakeup = <&pericfg 0x420 2>; > + wakeup-source; > + status = "disabled"; > + }; > + }; > + > mmc0: mmc@11230000 { > compatible = "mediatek,mt8186-mmc", > "mediatek,mt8183-mmc"; > @@ -939,6 +976,44 @@ > status = "disabled"; > }; > > + ssusb1: usb@11281000 { > + compatible = "mediatek,mt8186-mtu3", > + "mediatek,mtu3"; > + reg = <0 0x11281000 0 0x2dff>, > + <0 0x11283e00 0 0x0100>; > + reg-names = "mac", "ippc"; > + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, > + <&clk26m>; > + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; > + phys = <&u2port1 PHY_TYPE_USB2>, > + <&u3port1 PHY_TYPE_USB3>; phys fit in one line. Regards, Angelo
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add ADSP mailbox node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Il 18/01/23 10:18, Allen-KH Cheng ha scritto: > Add SPMI node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 3d88480913eb..a8ff984f1192 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -605,6 +605,25 @@ > clock-names = "spi", "wrap"; > }; > > + spmi: spmi@10015000 { > + compatible = "mediatek,mt8186-spmi", > + "mediatek,mt8195-spmi"; fits one line. > + reg = <0 0x10015000 0 0x000e00>, > + <0 0x1001B000 0 0x000100>; ditto Regards, Angelo
On 18/01/2023 10:18, Allen-KH Cheng wrote: > Add ADSP mailbox node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index a8ff984f1192..a0b7dacc10cd 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -640,6 +640,20 @@ > interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; > }; > > + adsp_mailbox0: mailbox@10686000 { > + compatible = "mediatek,mt8186-adsp-mbox"; > + #mbox-cells = <0>; > + reg = <0 0x10686100 0 0x1000>; > + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + adsp_mailbox1: mailbox@10687000 { > + compatible = "mediatek,mt8186-adsp-mbox"; > + #mbox-cells = <0>; > + reg = <0 0x10687100 0 0x1000>; > + interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > nor_flash: spi@11000000 { > compatible = "mediatek,mt8186-nor"; > reg = <0 0x11000000 0 0x1000>;
On 18/01/2023 10:18, Allen-KH Cheng wrote: > Add audio controller node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 2700c830316f..c52f9be1e750 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -998,6 +998,68 @@ > }; > }; > > + afe: audio-controller@11210000 { > + compatible = "mediatek,mt8186-sound"; > + reg = <0 0x11210000 0 0x2000>; > + clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, > + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, > + <&topckgen CLK_TOP_AUDIO>, > + <&topckgen CLK_TOP_AUD_INTBUS>, > + <&topckgen CLK_TOP_MAINPLL_D2_D4>, > + <&topckgen CLK_TOP_AUD_1>, > + <&apmixedsys CLK_APMIXED_APLL1>, > + <&topckgen CLK_TOP_AUD_2>, > + <&apmixedsys CLK_APMIXED_APLL2>, > + <&topckgen CLK_TOP_AUD_ENGEN1>, > + <&topckgen CLK_TOP_APLL1_D8>, > + <&topckgen CLK_TOP_AUD_ENGEN2>, > + <&topckgen CLK_TOP_APLL2_D8>, > + <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, > + <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, > + <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, > + <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, > + <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, > + <&topckgen CLK_TOP_APLL12_CK_DIV0>, > + <&topckgen CLK_TOP_APLL12_CK_DIV1>, > + <&topckgen CLK_TOP_APLL12_CK_DIV2>, > + <&topckgen CLK_TOP_APLL12_CK_DIV4>, > + <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, > + <&topckgen CLK_TOP_AUDIO_H>, > + <&clk26m>; > + clock-names = "aud_infra_clk", > + "mtkaif_26m_clk", > + "top_mux_audio", > + "top_mux_audio_int", > + "top_mainpll_d2_d4", > + "top_mux_aud_1", > + "top_apll1_ck", > + "top_mux_aud_2", > + "top_apll2_ck", > + "top_mux_aud_eng1", > + "top_apll1_d8", > + "top_mux_aud_eng2", > + "top_apll2_d8", > + "top_i2s0_m_sel", > + "top_i2s1_m_sel", > + "top_i2s2_m_sel", > + "top_i2s4_m_sel", > + "top_tdm_m_sel", > + "top_apll12_div0", > + "top_apll12_div1", > + "top_apll12_div2", > + "top_apll12_div4", > + "top_apll12_div_tdm", > + "top_mux_audio_h", > + "top_clk26m_clk"; > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; > + mediatek,apmixedsys = <&apmixedsys>; > + mediatek,infracfg = <&infracfg_ao>; > + mediatek,topckgen = <&topckgen>; > + resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; > + reset-names = "audiosys"; > + status = "disabled"; > + }; > + > mmc0: mmc@11230000 { > compatible = "mediatek,mt8186-mmc", > "mediatek,mt8183-mmc";
On 18/01/2023 10:18, Allen-KH Cheng wrote: > Add DPI node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Tested-by: Chen-Yu Tsai <wenst@chromium.org> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index c52f9be1e750..45b9d6777929 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -1230,6 +1230,23 @@ > power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > }; > > + dpi: dpi@1400a000 { > + compatible = "mediatek,mt8186-dpi"; > + reg = <0 0x1400a000 0 0x1000>; > + clocks = <&topckgen CLK_TOP_DPI>, > + <&mmsys CLK_MM_DISP_DPI>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + assigned-clocks = <&topckgen CLK_TOP_DPI>; > + assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; > + status = "disabled"; > + > + port { > + dpi_out: endpoint { }; > + }; > + }; > + > dsi0: dsi@14013000 { > compatible = "mediatek,mt8186-dsi"; > reg = <0 0x14013000 0 0x1000>;
This series is based on matthias github, for-next. Changes since v1: - Remove the unnecessary trailing number - Add aliases for ovl* and rdma* Allen-KH Cheng (9): arm64: dts: mediatek: mt8186: Add MTU3 nodes dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi arm64: dts: mediatek: mt8186: Add SPMI node arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes arm64: dts: mediatek: mt8186: Add ADSP node arm64: dts: mediatek: mt8186: Add audio controller node arm64: dts: mediatek: mt8186: Add DPI node dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr arm64: dts: mediatek: mt8186: Add display nodes .../display/mediatek/mediatek,ccorr.yaml | 2 +- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 +- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 342 ++++++++++++++++++ 3 files changed, 351 insertions(+), 4 deletions(-)