diff mbox series

[V2,1/2] arm64: tegra: Populate address/size cells for Tegra234 I2C

Message ID 20230116120626.55942-1-jonathanh@nvidia.com
State Accepted
Headers show
Series [V2,1/2] arm64: tegra: Populate address/size cells for Tegra234 I2C | expand

Commit Message

Jon Hunter Jan. 16, 2023, 12:06 p.m. UTC 
Populate the address and size cells properties for the I2C devices on
Tegra234.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes V1->V2: Added address/size cells for i2c@c240000

 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Thierry Reding Jan. 17, 2023, 1:20 p.m. UTC | #1 
On Mon, Jan 16, 2023 at 12:06:25PM +0000, Jon Hunter wrote:
> Populate the address and size cells properties for the I2C devices on
> Tegra234.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> Changes V1->V2: Added address/size cells for i2c@c240000
> 
>  arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Both patches applied, though I had to reshuffle some of the regulators.
They should always be listed after the nodes with unit-addresses.

Thanks,
Thierry
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index d71b0b5b931c..242bf59711f8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -785,6 +785,8 @@  gen1_i2c: i2c@3160000 {
 			reg = <0x3160000 0x100>;
 			status = "disabled";
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			clock-frequency = <400000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C1
 				  &bpmp TEGRA234_CLK_PLLP_OUT0>;
@@ -803,6 +805,8 @@  cam_i2c: i2c@3180000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x3180000 0x100>;
 			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <400000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C3
@@ -822,6 +826,8 @@  dp_aux_ch1_i2c: i2c@3190000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x3190000 0x100>;
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <100000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C4
@@ -841,6 +847,8 @@  dp_aux_ch0_i2c: i2c@31b0000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x31b0000 0x100>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <100000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C6
@@ -860,6 +868,8 @@  dp_aux_ch2_i2c: i2c@31c0000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x31c0000 0x100>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <100000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C7
@@ -886,6 +896,8 @@  dp_aux_ch3_i2c: i2c@31e0000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x31e0000 0x100>;
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <100000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C9
@@ -1872,6 +1884,8 @@  gen2_i2c: i2c@c240000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0xc240000 0x100>;
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <100000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C2
@@ -1891,6 +1905,8 @@  gen8_i2c: i2c@c250000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0xc250000 0x100>;
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 			clock-frequency = <400000>;
 			clocks = <&bpmp TEGRA234_CLK_I2C8