| Message ID | 20221219231354.135626-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Fix incorrect annotation | expand |
On 12/19/22 16:13, juzhe.zhong@rivai.ai wrote: > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> > > gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix incorrect annotations. > (available_occurrence_p): Ditto. > (backward_propagate_worthwhile_p): Ditto. > (can_backward_propagate_p): Ditto. OK. And more generally, fixes like this don't need review. Consider them pre-approved for the future. jeff
On 12/19/22 17:38, juzhe.zhong wrote:
> Would you mind merging it for me？ I can‘t merge code.
Do you mean you do not have write access to the repository? If so, that
can be easily fixed.
https://sourceware.org/cgi-bin/pdw/ps_form.cgi
List me as your sponsor.
jeff
On Tue, 20 Dec 2022 08:02:56 PST (-0800), jeffreyalaw@gmail.com wrote: > > > On 12/19/22 17:38, juzhe.zhong wrote: >> Would you mind merging it for me？ I can‘t merge code. > Do you mean you do not have write access to the repository? If so, that > can be easily fixed. > > https://sourceware.org/cgi-bin/pdw/ps_form.cgi > > List me as your sponsor. Do we also need to add him to the write after approval section in MAINTAINERS? We were trying to remember how to do this on IRC last night...
On 12/20/22 09:06, Palmer Dabbelt wrote: > On Tue, 20 Dec 2022 08:02:56 PST (-0800), jeffreyalaw@gmail.com wrote: >> >> >> On 12/19/22 17:38, juzhe.zhong wrote: >>> Would you mind merging it for me？ I can‘t merge code. >> Do you mean you do not have write access to the repository? If so, that >> can be easily fixed. >> >> https://sourceware.org/cgi-bin/pdw/ps_form.cgi >> >> List me as your sponsor. > > Do we also need to add him to the write after approval section in > MAINTAINERS? We were trying to remember how to do this on IRC last > night... That's the first TODO once his write access is set up. Jeff
Thanks. I received an email from sourceware: "You should now have write access to the source control repository for your project." It seems that I can merge codes? However, I still don't know how to merge codes. juzhe.zhong@rivai.ai From: Jeff Law Date: 2022-12-21 00:02 To: juzhe.zhong CC: gcc-patches@gcc.gnu.org; kito.cheng@gmail.com; palmer@dabbelt.com Subject: Re: [PATCH] RISC-V: Fix incorrect annotation On 12/19/22 17:38, juzhe.zhong wrote: > Would you mind merging it for me？ I can‘t merge code. Do you mean you do not have write access to the repository? If so, that can be easily fixed. https://sourceware.org/cgi-bin/pdw/ps_form.cgi List me as your sponsor. jeff
On Tue, 20 Dec 2022 15:33:11 PST (-0800), juzhe.zhong@rivai.ai wrote: > Thanks. I received an email from sourceware: > "You should now have write access to the source control repository for your project." > It seems that I can merge codes? However, I still don't know how to merge codes. You should have a sourceware account, along with an associated private key. With those you should be able to get push access via https://gcc.gnu.org/gitwrite.html > > > juzhe.zhong@rivai.ai > > From: Jeff Law > Date: 2022-12-21 00:02 > To: juzhe.zhong > CC: gcc-patches@gcc.gnu.org; kito.cheng@gmail.com; palmer@dabbelt.com > Subject: Re: [PATCH] RISC-V: Fix incorrect annotation > > > On 12/19/22 17:38, juzhe.zhong wrote: >> Would you mind merging it for me？ I can‘t merge code. > Do you mean you do not have write access to the repository? If so, that > can be easily fixed. > > https://sourceware.org/cgi-bin/pdw/ps_form.cgi > > List me as your sponsor. > > jeff >
Committed, thanks :) Ju-Zhe has not figured out how to commit to his environment yet, I am helping him to set up. On Wed, Dec 21, 2022 at 7:38 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Tue, 20 Dec 2022 15:33:11 PST (-0800), juzhe.zhong@rivai.ai wrote: > > Thanks. I received an email from sourceware: > > "You should now have write access to the source control repository for your project." > > It seems that I can merge codes? However, I still don't know how to merge codes. > > You should have a sourceware account, along with an associated private > key. With those you should be able to get push access via > https://gcc.gnu.org/gitwrite.html > > > > > > > juzhe.zhong@rivai.ai > > > > From: Jeff Law > > Date: 2022-12-21 00:02 > > To: juzhe.zhong > > CC: gcc-patches@gcc.gnu.org; kito.cheng@gmail.com; palmer@dabbelt.com > > Subject: Re: [PATCH] RISC-V: Fix incorrect annotation > > > > > > On 12/19/22 17:38, juzhe.zhong wrote: > >> Would you mind merging it for me？ I can‘t merge code. > > Do you mean you do not have write access to the repository? If so, that > > can be easily fixed. > > > > https://sourceware.org/cgi-bin/pdw/ps_form.cgi > > > > List me as your sponsor. > > > > jeff > >
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 0c2ff630e96..72f1e4059ab 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -186,7 +186,7 @@ anticipatable_occurrence_p (const insn_info *insn, const vector_insn_info dem) /* The only possible operand we care of VSETVL is AVL. */ if (dem.has_avl_reg ()) { - /* The operands shoule not be modified in the basic block prior + /* The operands should not be modified in the basic block prior to the occurrence. */ if (!vlmax_avl_p (dem.get_avl ())) { @@ -223,7 +223,7 @@ available_occurrence_p (const insn_info *insn, const vector_insn_info dem) /* The only possible operand we care of VSETVL is AVL. */ if (dem.has_avl_reg ()) { - /* The operands shoule not be modified in the basic block prior + /* The operands should not be modified in the basic block prior to the occurrence. e.g. bb: @@ -284,7 +284,7 @@ backward_propagate_worthwhile_p (const basic_block cfg_bb, |_________| reaching_out Header is incompatible with reaching_out and the block is loop itself, - we don't backward propagete the local_dem since we can't avoid emit + we don't backward propagate the local_dem since we can't avoid emit vsetvl for the local_dem. */ edge e; edge_iterator ei; @@ -334,10 +334,10 @@ can_backward_propagate_p (const function_info *ssa, const basic_block cfg_bb, insn_info *insn = prop.get_insn (); /* TODO: We don't backward propagate the explict VSETVL here - since we will change vsetvl and vsetvlmax intrinsiscs into - no side effects which can be optimized into optimzal location - by GCC internal PASSes. We only need to support these backward - propagation if vsetvl instrinsics have side effects. */ + since we will change vsetvl and vsetvlmax intrinsics into + no side effects which can be optimized into optimal location + by GCC internal passes. We only need to support these backward + propagation if vsetvl intrinsics have side effects. */ if (vsetvl_insn_p (insn->rtl ())) return false; @@ -369,7 +369,7 @@ can_backward_propagate_p (const function_info *ssa, const basic_block cfg_bb, def_info *def = find_access (insn->uses (), REGNO (reg))->def (); /* If the definition is in the current block, we can't propagate it - acrocss blocks. */ + across blocks. */ if (def->bb ()->cfg_bb ()->index == insn->bb ()->cfg_bb ()->index) { set_info *set = safe_dyn_cast<set_info *> (def); @@ -406,7 +406,7 @@ can_backward_propagate_p (const function_info *ssa, const basic_block cfg_bb, if (def->bb ()->cfg_bb ()->index == cfg_bb->index) return true; - /* Make sure we don't backward propagete the VL/VTYPE info over the + /* Make sure we don't backward propagate the VL/VTYPE info over the definition blocks. */ bool visited_p = false; for (const bb_info *bb : ssa->reverse_bbs ())
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix incorrect annotations. (available_occurrence_p): Ditto. (backward_propagate_worthwhile_p): Ditto. (can_backward_propagate_p): Ditto. --- gcc/config/riscv/riscv-vsetvl.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)