| Message ID | 20221207220012.16529-1-quic_bjorande@quicinc.com |
|---|---|
| Headers | show |
| Series | drm/msm: Add SC8280XP support | expand |
On 08/12/2022 00:00, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 > interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the > necessary definitions and describe the DPU in the SC8280XP. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - Fix highest_bank_bit, based on downstream > - Add ubwc_swizzle > - Use CTL_SC7280_MASK instead of listing the bits directly > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > In the SC8280XP platform there are two identical MDSS instances, each > with the same set of DisplayPort instances, at different addresses. > > By not relying on the index to define the instance id it's possible to > describe them both in the same table and hence have a single compatible. > > While at it, flatten the cfg/desc structure so that the match data is > just an array of descs. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - None > > drivers/gpu/drm/msm/dp/dp_display.c | 72 ++++++++++------------------- > 1 file changed, 25 insertions(+), 47 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index 7ff60e5ff325..eeb292f1ad1b 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -122,61 +122,41 @@ struct dp_display_private { > > struct msm_dp_desc { > phys_addr_t io_start; > + unsigned int id; > unsigned int connector_type; > bool wide_bus_en; > }; > > -struct msm_dp_config { > - const struct msm_dp_desc *descs; > - size_t num_descs; > -}; > - > static const struct msm_dp_desc sc7180_dp_descs[] = { > - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > -}; > - > -static const struct msm_dp_config sc7180_dp_cfg = { > - .descs = sc7180_dp_descs, > - .num_descs = ARRAY_SIZE(sc7180_dp_descs), > + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > + {} > }; > > static const struct msm_dp_desc sc7280_dp_descs[] = { > - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > -}; > - > -static const struct msm_dp_config sc7280_dp_cfg = { > - .descs = sc7280_dp_descs, > - .num_descs = ARRAY_SIZE(sc7280_dp_descs), > + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > + {} > }; > > static const struct msm_dp_desc sc8180x_dp_descs[] = { > - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > - [MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP }, > -}; > - > -static const struct msm_dp_config sc8180x_dp_cfg = { > - .descs = sc8180x_dp_descs, > - .num_descs = ARRAY_SIZE(sc8180x_dp_descs), > + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > + { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > + { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP }, > + {} > }; > > static const struct msm_dp_desc sm8350_dp_descs[] = { > - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > -}; > - > -static const struct msm_dp_config sm8350_dp_cfg = { > - .descs = sm8350_dp_descs, > - .num_descs = ARRAY_SIZE(sm8350_dp_descs), > + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > + {} > }; > > static const struct of_device_id dp_dt_match[] = { > - { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg }, > - { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_cfg }, > - { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, > - { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, > - { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg }, > - { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_cfg }, > + { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_descs }, > + { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_descs }, > + { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs }, > + { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs }, > + { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs }, > + { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_descs }, > {} > }; > > @@ -1262,10 +1242,9 @@ int dp_display_request_irq(struct msm_dp *dp_display) > return 0; > } > > -static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pdev, > - unsigned int *id) > +static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pdev) > { > - const struct msm_dp_config *cfg = of_device_get_match_data(&pdev->dev); > + const struct msm_dp_desc *descs = of_device_get_match_data(&pdev->dev); > struct resource *res; > int i; > > @@ -1273,11 +1252,9 @@ static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pde > if (!res) > return NULL; > > - for (i = 0; i < cfg->num_descs; i++) { > - if (cfg->descs[i].io_start == res->start) { > - *id = i; > - return &cfg->descs[i]; > - } > + for (i = 0; i < descs[i].io_start; i++) { > + if (descs[i].io_start == res->start) > + return &descs[i]; > } > > dev_err(&pdev->dev, "unknown displayport instance\n"); > @@ -1299,12 +1276,13 @@ static int dp_display_probe(struct platform_device *pdev) > if (!dp) > return -ENOMEM; > > - desc = dp_display_get_desc(pdev, &dp->id); > + desc = dp_display_get_desc(pdev); > if (!desc) > return -EINVAL; > > dp->pdev = pdev; > dp->name = "drm_dp"; > + dp->id = desc->id; > dp->dp_display.connector_type = desc->connector_type; > dp->wide_bus_en = desc->wide_bus_en; > dp->dp_display.is_edp =
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SC8280XP platform has four DisplayPort controllers, per MDSS > instance, all with widebus support. > > The first two are defined to be DisplayPort only, while the latter pair > (of each instance) can be either DisplayPort or Embedded DisplayPort. > The two sets are tied to the possible compatibels. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - None > > drivers/gpu/drm/msm/dp/dp_display.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index eeb292f1ad1b..5b7f1f885b2f 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -145,6 +145,26 @@ static const struct msm_dp_desc sc8180x_dp_descs[] = { > {} > }; > > +static const struct msm_dp_desc sc8280xp_dp_descs[] = { > + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, > + {} > +}; > + > +static const struct msm_dp_desc sc8280xp_edp_descs[] = { > + { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > + { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > + { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, > + {} > +}; > + > static const struct msm_dp_desc sm8350_dp_descs[] = { > { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, > {} > @@ -156,6 +176,8 @@ static const struct of_device_id dp_dt_match[] = { > { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs }, > { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs }, > { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs }, > + { .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs }, > + { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_edp_descs }, > { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_descs }, > {} > };
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The Qualcomm SDM845 platform has a single DisplayPort controller, with > the same design as SC7180, so add support for this by reusing the SC7180 > definition. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - None > > drivers/gpu/drm/msm/dp/dp_display.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index 5b7f1f885b2f..666b45c8ab80 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -178,6 +178,7 @@ static const struct of_device_id dp_dt_match[] = { > { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs }, > { .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs }, > { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_edp_descs }, > + { .compatible = "qcom,sdm845-dp", .data = &sc7180_dp_descs }, > { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_descs }, > {} > };
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The DisplayPort controller's internal HPD interrupt handling is used for > cases where the HPD signal is connected to a GPIO which is pinmuxed into > the DisplayPort controller. In other configurations the HPD notification > might be delivered by the DRM framework from an associated bridge. > > This difference is not appropriately represented by the "is_edp" > boolean, but is properly represented by the frameworks invocation of the > hpd_enable() and hpd_disable() callbacks. Switch the current condition > to rely on these callbacks instead. > > This ensures appropriate handling of the three cases; no bridge > connected, a bridge without DRM_BRIDGE_OP_HPD and a bridge with > DRM_BRIDGE_OP_HPD. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - Reordered the hpd_enable/disable patch earlier > - Squashed in internal_hpd conditional changes into the same patch > > drivers/gpu/drm/msm/dp/dp_display.c | 40 +++++++++++++++++++++-------- > drivers/gpu/drm/msm/dp/dp_display.h | 1 + > drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++ > drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++ > 4 files changed, 35 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index 666b45c8ab80..095adf528e43 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -610,8 +610,10 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) > } > > /* enable HDP irq_hpd/replug interrupt */ > - dp_catalog_hpd_config_intr(dp->catalog, > - DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); > + if (dp->dp_display.internal_hpd) > + dp_catalog_hpd_config_intr(dp->catalog, > + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, > + true); > > drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", > dp->dp_display.connector_type, state); > @@ -651,8 +653,10 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) > dp->dp_display.connector_type, state); > > /* disable irq_hpd/replug interrupts */ > - dp_catalog_hpd_config_intr(dp->catalog, > - DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); > + if (dp->dp_display.internal_hpd) > + dp_catalog_hpd_config_intr(dp->catalog, > + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, > + false); > > /* unplugged, no more irq_hpd handle */ > dp_del_event(dp, EV_IRQ_HPD_INT); > @@ -678,7 +682,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) > } > > /* disable HPD plug interrupts */ > - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); > + if (dp->dp_display.internal_hpd) > + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); > > /* > * We don't need separate work for disconnect as > @@ -696,7 +701,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) > dp_display_handle_plugged_change(&dp->dp_display, false); > > /* enable HDP plug interrupt to prepare for next plugin */ > - if (!dp->dp_display.is_edp) > + if (dp->dp_display.internal_hpd) > dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true); > > drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", > @@ -1081,8 +1086,8 @@ static void dp_display_config_hpd(struct dp_display_private *dp) > dp_display_host_init(dp); > dp_catalog_ctrl_hpd_config(dp->catalog); > > - /* Enable plug and unplug interrupts only for external DisplayPort */ > - if (!dp->dp_display.is_edp) > + /* Enable plug and unplug interrupts only if requested */ > + if (dp->dp_display.internal_hpd) > dp_catalog_hpd_config_intr(dp->catalog, > DP_DP_HPD_PLUG_INT_MASK | > DP_DP_HPD_UNPLUG_INT_MASK, > @@ -1374,8 +1379,7 @@ static int dp_pm_resume(struct device *dev) > > dp_catalog_ctrl_hpd_config(dp->catalog); > > - > - if (!dp->dp_display.is_edp) > + if (dp->dp_display.internal_hpd) > dp_catalog_hpd_config_intr(dp->catalog, > DP_DP_HPD_PLUG_INT_MASK | > DP_DP_HPD_UNPLUG_INT_MASK, > @@ -1772,3 +1776,19 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge, > dp_display->dp_mode.h_active_low = > !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); > } > + > +void dp_bridge_hpd_enable(struct drm_bridge *bridge) > +{ > + struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); > + struct msm_dp *dp_display = dp_bridge->dp_display; > + > + dp_display->internal_hpd = true; > +} > + > +void dp_bridge_hpd_disable(struct drm_bridge *bridge) > +{ > + struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); > + struct msm_dp *dp_display = dp_bridge->dp_display; > + > + dp_display->internal_hpd = false; > +} > diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h > index dcedf021f7fe..371337d0fae2 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.h > +++ b/drivers/gpu/drm/msm/dp/dp_display.h > @@ -21,6 +21,7 @@ struct msm_dp { > bool power_on; > unsigned int connector_type; > bool is_edp; > + bool internal_hpd; > > hdmi_codec_plugged_cb plugged_cb; > > diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c > index 6db82f9b03af..9d03b6ee3c41 100644 > --- a/drivers/gpu/drm/msm/dp/dp_drm.c > +++ b/drivers/gpu/drm/msm/dp/dp_drm.c > @@ -102,6 +102,8 @@ static const struct drm_bridge_funcs dp_bridge_ops = { > .get_modes = dp_bridge_get_modes, > .detect = dp_bridge_detect, > .atomic_check = dp_bridge_atomic_check, > + .hpd_enable = dp_bridge_hpd_enable, > + .hpd_disable = dp_bridge_hpd_disable, > }; > > struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, > diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h > index 82035dbb0578..1f871b555006 100644 > --- a/drivers/gpu/drm/msm/dp/dp_drm.h > +++ b/drivers/gpu/drm/msm/dp/dp_drm.h > @@ -32,5 +32,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, > void dp_bridge_mode_set(struct drm_bridge *drm_bridge, > const struct drm_display_mode *mode, > const struct drm_display_mode *adjusted_mode); > +void dp_bridge_hpd_enable(struct drm_bridge *bridge); > +void dp_bridge_hpd_disable(struct drm_bridge *bridge); > > #endif /* _DP_DRM_H_ */
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The DisplayPort controller's hot-plug mechanism is based on pinmuxing a > physical signal on a GPIO pin into the controller. This is not always > possible, either because there aren't dedicated GPIOs available or > because the hot-plug signal is a virtual notification, in cases such as > USB Type-C. > > For these cases, by implementing the hpd_notify() callback for the > DisplayPort controller's drm_bridge, a downstream drm_bridge > (next_bridge) can be used to track and signal the connection status > changes. > > This makes it possible to use downstream drm_bridges such as > display-connector or any virtual mechanism, as long as they are > implemented as a drm_bridge. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > [bjorn: Drop connector->fwnode assignment and dev from struct msm_dp] > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - Look at internal_hpd now that it's introduced before this patch. > > drivers/gpu/drm/msm/dp/dp_display.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/msm/dp/dp_drm.c | 1 + > drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++ > 3 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index 095adf528e43..0bee412603fe 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -1792,3 +1792,25 @@ void dp_bridge_hpd_disable(struct drm_bridge *bridge) > > dp_display->internal_hpd = false; > } > + > +void dp_bridge_hpd_notify(struct drm_bridge *bridge, > + enum drm_connector_status status) > +{ > + struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); > + struct msm_dp *dp_display = dp_bridge->dp_display; > + struct dp_display_private *dp = container_of(dp_display, struct dp_display_private, dp_display); > + > + /* Without next_bridge interrupts are handled by the DP core directly */ > + if (dp_display->internal_hpd) > + return; > + > + if (!dp->core_initialized) { > + drm_dbg_dp(dp->drm_dev, "not initialized\n"); > + return; > + } > + > + if (!dp_display->is_connected && status == connector_status_connected) > + dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); > + else if (dp_display->is_connected && status == connector_status_disconnected) > + dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); > +} > diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c > index 9d03b6ee3c41..275370f21115 100644 > --- a/drivers/gpu/drm/msm/dp/dp_drm.c > +++ b/drivers/gpu/drm/msm/dp/dp_drm.c > @@ -104,6 +104,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = { > .atomic_check = dp_bridge_atomic_check, > .hpd_enable = dp_bridge_hpd_enable, > .hpd_disable = dp_bridge_hpd_disable, > + .hpd_notify = dp_bridge_hpd_notify, > }; > > struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, > diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h > index 1f871b555006..250f7c66201f 100644 > --- a/drivers/gpu/drm/msm/dp/dp_drm.h > +++ b/drivers/gpu/drm/msm/dp/dp_drm.h > @@ -34,5 +34,7 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge, > const struct drm_display_mode *adjusted_mode); > void dp_bridge_hpd_enable(struct drm_bridge *bridge); > void dp_bridge_hpd_disable(struct drm_bridge *bridge); > +void dp_bridge_hpd_notify(struct drm_bridge *bridge, > + enum drm_connector_status status); > > #endif /* _DP_DRM_H_ */
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 > interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the > necessary definitions and describe the DPU in the SC8280XP. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - Fix highest_bank_bit, based on downstream > - Add ubwc_swizzle > - Use CTL_SC7280_MASK instead of listing the bits directly > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > drivers/gpu/drm/msm/msm_drv.h | 1 + > 7 files changed, 243 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 2196e205efa5..0315fe68af2f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -124,6 +124,19 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + BIT(MDP_INTF4_7xxx_INTR) | \ > + BIT(MDP_INTF5_7xxx_INTR) | \ > + BIT(MDP_INTF6_7xxx_INTR) | \ > + BIT(MDP_INTF7_7xxx_INTR) | \ > + BIT(MDP_INTF8_7xxx_INTR)) > + > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > @@ -365,6 +378,20 @@ static const struct dpu_caps sc8180x_dpu_caps = { > .max_vdeci_exp = MAX_VERT_DECIMATION, > }; > > +static const struct dpu_caps sc8280xp_dpu_caps = { > + .max_mixer_width = 2560, > + .max_mixer_blendstages = 11, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 5120, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8250_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -545,6 +572,25 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sc8280xp_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 2, > + .ubwc_swizzle = 6, > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg qcm2290_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -648,6 +694,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sc8280xp_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x204, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sm8150_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -926,6 +1011,33 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { > sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = > + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 = > + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 = > + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 = > + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); > + > +static const struct dpu_sspp_cfg sc8280xp_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, > + sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, > + sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, > + sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, > + sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > > #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ > { \ > @@ -1034,6 +1146,17 @@ static const struct dpu_lm_cfg sc7180_lm[] = { > &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), > }; > > +/* SC8280XP */ > + > +static const struct dpu_lm_cfg sc8280xp_lm[] = { > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), > + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), > + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), > + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), > + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), > +}; > + > /* SM8150 */ > > static const struct dpu_lm_cfg sm8150_lm[] = { > @@ -1192,6 +1315,21 @@ static struct dpu_pingpong_cfg sc7180_pp[] = { > PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), > }; > > +static struct dpu_pingpong_cfg sc8280xp_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), > + PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), > + PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), > + PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), > + PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), > +}; > + > static const struct dpu_pingpong_cfg sm8150_pp[] = { > PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > @@ -1243,6 +1381,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > +}; > + > /************************************************************* > * DSC sub blocks config > *************************************************************/ > @@ -1317,6 +1461,19 @@ static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > }; > > +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ > +static const struct dpu_intf_cfg sc8280xp_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > + INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21), > + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > + INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17), > + INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19), > + INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13), > +}; > + > static const struct dpu_intf_cfg qcm2290_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -1419,6 +1576,14 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { > }, > }; > > +static const struct dpu_reg_dma_cfg sc8280xp_regdma = { > + .base = 0x0, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > static const struct dpu_reg_dma_cfg sdm845_regdma = { > .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c > }; > @@ -1690,6 +1855,33 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { > .min_llcc_ib = 800000, > .min_dram_ib = 800000, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > +static const struct dpu_perf_cfg sc8280xp_perf_data = { > + .max_bw_low = 13600000, > + .max_bw_high = 18200000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .danger_lut_tbl = {0xf, 0xffff, 0x0}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc8180x_qos_linear), > .entries = sc8180x_qos_linear > @@ -1937,6 +2129,30 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { > .mdss_irqs = IRQ_SC8180X_MASK, > }; > > +static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = { > + .caps = &sc8280xp_dpu_caps, > + .mdp_count = ARRAY_SIZE(sc8280xp_mdp), > + .mdp = sc8280xp_mdp, > + .ctl_count = ARRAY_SIZE(sc8280xp_ctl), > + .ctl = sc8280xp_ctl, > + .sspp_count = ARRAY_SIZE(sc8280xp_sspp), > + .sspp = sc8280xp_sspp, > + .mixer_count = ARRAY_SIZE(sc8280xp_lm), > + .mixer = sc8280xp_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sc8280xp_pp), > + .pingpong = sc8280xp_pp, > + .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), > + .merge_3d = sc8280xp_merge_3d, > + .intf_count = ARRAY_SIZE(sc8280xp_intf), > + .intf = sc8280xp_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .perf = &sc8280xp_perf_data, > + .mdss_irqs = IRQ_SC8280XP_MASK, > +}; > + > static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .caps = &sm8250_dpu_caps, > .mdp_count = ARRAY_SIZE(sm8250_mdp), > @@ -2024,6 +2240,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg}, > }; > > const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 3b645d5aa9aa..6897b35c18fa 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -47,6 +47,7 @@ > #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > +#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ > > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) > #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index cf1b6d84c18a..27d74c4d8a98 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -35,6 +35,9 @@ > #define MDP_INTF_3_OFF_REV_7xxx 0x37000 > #define MDP_INTF_4_OFF_REV_7xxx 0x38000 > #define MDP_INTF_5_OFF_REV_7xxx 0x39000 > +#define MDP_INTF_6_OFF_REV_7xxx 0x3a000 > +#define MDP_INTF_7_OFF_REV_7xxx 0x3b000 > +#define MDP_INTF_8_OFF_REV_7xxx 0x3c000 > > /** > * struct dpu_intr_reg - array of DPU register sets > @@ -139,6 +142,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = { > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS > }, > + [MDP_INTF6_7xxx_INTR] = { > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > + [MDP_INTF7_7xxx_INTR] = { > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > + [MDP_INTF8_7xxx_INTR] = { > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > }; > > #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > index 46443955443c..425465011c80 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > @@ -31,6 +31,9 @@ enum dpu_hw_intr_reg { > MDP_INTF3_7xxx_INTR, > MDP_INTF4_7xxx_INTR, > MDP_INTF5_7xxx_INTR, > + MDP_INTF6_7xxx_INTR, > + MDP_INTF7_7xxx_INTR, > + MDP_INTF8_7xxx_INTR, > MDP_INTR_MAX, > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index d3b0ed0a9c6c..d595096a4b1f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -214,6 +214,8 @@ enum dpu_intf { > INTF_4, > INTF_5, > INTF_6, > + INTF_7, > + INTF_8, > INTF_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index b71199511a52..30f894864cca 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1292,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc7180-dpu", }, > { .compatible = "qcom,sc7280-dpu", }, > { .compatible = "qcom,sc8180x-dpu", }, > + { .compatible = "qcom,sc8280xp-dpu", }, > { .compatible = "qcom,sm6115-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index d4e0ef608950..b2789efd59e8 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -61,6 +61,7 @@ enum msm_dp_controller { > MSM_DP_CONTROLLER_0, > MSM_DP_CONTROLLER_1, > MSM_DP_CONTROLLER_2, > + MSM_DP_CONTROLLER_3, > MSM_DP_CONTROLLER_COUNT, > }; >
On 12/7/2022 2:00 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > Add compatible for the SC8280XP Mobile Display Subsystem and > initialization for version 8.0.0. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > Changes since v4: > - None > > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 86b28add1fff..8677e74868cf 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -287,6 +287,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > + case DPU_HW_VER_800: > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 2, 1); > + break; > } > > return ret; > @@ -513,6 +516,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc7180-mdss" }, > { .compatible = "qcom,sc7280-mdss" }, > { .compatible = "qcom,sc8180x-mdss" }, > + { .compatible = "qcom,sc8280xp-mdss" }, > { .compatible = "qcom,sm6115-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" },
On Wed, Dec 7, 2022 at 4:00 PM Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > This introduces support for the SC8280XP platform in the MDSS, DPU and > DP driver. It reworks the HDP handling in the DP driver to support > external HPD sources - such as the dp-connector, or USB Type-C altmode. > > It then introduces the display clock controllers, mdss, dpu and > displayport controllers and link everything together, for both the MDSS > instances on the platform, and lastly enables EDP on the compute > reference device and 6 of the MiniDP outputs on the automotive > development platform. > > > The patches was previously sent separately, but submitting them together > here as they (except dts addition) goes in the same tree. > > Bjorn Andersson (12): > dt-bindings: display/msm: Add binding for SC8280XP MDSS > drm/msm/dpu: Introduce SC8280XP > drm/msm: Introduce SC8280XP MDSS > dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles > drm/msm/dp: Stop using DP id as index in desc > drm/msm/dp: Add DP and EDP compatibles for SC8280XP > drm/msm/dp: Add SDM845 DisplayPort instance > drm/msm/dp: Rely on hpd_enable/disable callbacks > drm/msm/dp: Implement hpd_notify() > arm64: dts: qcom: sc8280xp: Define some of the display blocks > arm64: dts: qcom: sc8280xp-crd: Enable EDP > arm64: dts: qcom: sa8295-adp: Enable DP instances > > .../bindings/display/msm/dp-controller.yaml | 3 + > .../display/msm/qcom,sc8280xp-dpu.yaml | 122 +++ > .../display/msm/qcom,sc8280xp-mdss.yaml | 143 +++ > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++- > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 +- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 +++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 + > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > drivers/gpu/drm/msm/dp/dp_display.c | 151 ++-- > drivers/gpu/drm/msm/dp/dp_display.h | 1 + > drivers/gpu/drm/msm/dp/dp_drm.c | 3 + > drivers/gpu/drm/msm/dp/dp_drm.h | 4 + > drivers/gpu/drm/msm/msm_drv.h | 1 + > drivers/gpu/drm/msm/msm_mdss.c | 4 + > 18 files changed, 1770 insertions(+), 57 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml > > -- > 2.37.3 > Tested on Lenovo Thinkpad X13s Tested-by: Steev Klimaszewski <steev@kali.org>
On Wed, Dec 07, 2022 at 02:00:11PM -0800, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes > and link it together with the backlight control. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++++++++++++++++++++++- > 1 file changed, 71 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > index f09810e3d956..a7d2384cbbe8 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > @@ -20,7 +20,7 @@ aliases { > serial0 = &qup2_uart17; > }; > > - backlight { > + backlight: backlight { > compatible = "pwm-backlight"; > pwms = <&pmc8280c_lpg 3 1000000>; > enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; > @@ -34,6 +34,22 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + vreg_edp_3p3: regulator-edp-3p3 { > + compatible = "regulator-fixed"; > + > + regulator-name = "VREG_EDP_3P3"; Please use the net name from the schematics here (i.e. "VCC3LCD"). > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&edp_reg_en>; > + > + regulator-boot-on; > + }; > + > vreg_edp_bl: regulator-edp-bl { > compatible = "regulator-fixed"; > > @@ -230,6 +246,54 @@ vreg_l9d: ldo9 { > }; > }; > > +&dispcc0 { > + status = "okay"; > +}; > + > +&mdss0 { > + status = "okay"; > +}; > + > +&mdss0_dp3 { > + compatible = "qcom,sc8280xp-edp"; > + status = "okay"; Please move the status property last (i.e. after data-lanes). > + > + data-lanes = <0 1 2 3>; > + > + aux-bus { > + panel { > + compatible = "edp-panel"; > + power-supply = <&vreg_edp_3p3>; > + > + backlight = <&backlight>; > + > + ports { > + port { > + edp_panel_in: endpoint { > + remote-endpoint = <&mdss0_dp3_out>; > + }; > + }; > + }; > + }; > + }; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp3_out: endpoint { > + remote-endpoint = <&edp_panel_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp3_phy { > + status = "okay"; Same here. > + > + vdda-phy-supply = <&vreg_l6b>; > + vdda-pll-supply = <&vreg_l3b>; > +}; > + > &pcie2a { > perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; > @@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state { > &tlmm { > gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; > > + edp_reg_en: edp-reg-en-state { > + pins = "gpio25"; > + function = "gpio"; > + output-enable; 'output-enable' is not valid for tlmm and causes the settings to be rejected: sc8280xp-tlmm f100000.pinctrl: pin_config_group_set op failed for group 25 reg-fixed-voltage regulator-edp-3p3: Error applying setting, reverse things back > + }; > + > kybd_default: kybd-default-state { > disable-pins { > pins = "gpio102"; Johan
On Wed, Dec 07, 2022 at 02:00:12PM -0800, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SA8295P ADP has, among other interfaces, six MiniDP connectors which > are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. > > Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, > DP PHYs and link them all together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++++++++++++++++++++- > 1 file changed, 241 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > index 6c29d7d757e0..d55c8c5304cc 100644 > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +&mdss0_dp2 { > + status = "okay"; Please move 'status' last. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp2_phy_out: endpoint { > + remote-endpoint = <&edp0_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp2_phy { > + status = "okay"; Same here. > + > + vdda-phy-supply = <&vreg_l8g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss0_dp3 { > + status = "okay"; And here. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp3_phy_out: endpoint { > + remote-endpoint = <&edp1_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp3_phy { > + status = "okay"; And here. > + > + vdda-phy-supply = <&vreg_l8g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1 { > + status = "okay"; > +}; > + > +&mdss1_dp0 { > + status = "okay"; And here. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp0_phy_out: endpoint { > + remote-endpoint = <&dp2_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp0_phy { > + status = "okay"; Ditto. > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp1 { > + status = "okay"; Ditto. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp1_phy_out: endpoint { > + remote-endpoint = <&dp3_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp1_phy { > + status = "okay"; Ditto. > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp2 { > + status = "okay"; Ditto. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp2_phy_out: endpoint { > + remote-endpoint = <&edp2_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp2_phy { > + status = "okay"; Ditto. > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp3 { > + status = "okay"; Ditto. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp3_phy_out: endpoint { > + remote-endpoint = <&edp3_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp3_phy { > + status = "okay"; Ditto. > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > &pcie2a { > perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; Johan
On Wed, Dec 07, 2022 at 02:00:10PM -0800, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > Define the display clock controllers, the MDSS instances, the DP phys > and connect these together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > 1 file changed, 838 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 9f3132ac2857..c2f186495506 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > + mdss0: display-subsystem@ae00000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc0 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + status = "disabled"; Please move status last. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss0_mdp: display-controller@ae01000 { [...] > + mdss1: display-subsystem@22000000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x22000000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc1 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1800 0x402>; > + > + status = "disabled"; Same here. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss1_mdp: display-controller@22001000 { Johan
On Thu, 8 Dec 2022 at 00:00, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes > and link it together with the backlight control. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++++++++++++++++++++++- > 1 file changed, 71 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > index f09810e3d956..a7d2384cbbe8 100644 [skipped] > @@ -230,6 +246,54 @@ vreg_l9d: ldo9 { > }; > }; > > +&dispcc0 { > + status = "okay"; > +}; > + > +&mdss0 { > + status = "okay"; > +}; > + > +&mdss0_dp3 { > + compatible = "qcom,sc8280xp-edp"; > + status = "okay"; > + > + data-lanes = <0 1 2 3>; I hope to land Kuogee patches that move data-lanes to the endpoint node, where they belong. Do we have any good way to proceed here? Or would it be easier to land this patch as is and then, maybe next cycle, move the property? > + > + aux-bus { > + panel { > + compatible = "edp-panel"; > + power-supply = <&vreg_edp_3p3>; > + > + backlight = <&backlight>; > + > + ports { > + port { > + edp_panel_in: endpoint { > + remote-endpoint = <&mdss0_dp3_out>; > + }; > + }; > + }; > + }; > + }; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp3_out: endpoint { > + remote-endpoint = <&edp_panel_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp3_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l6b>; > + vdda-pll-supply = <&vreg_l3b>; > +}; > + > &pcie2a { > perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; > @@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state { > &tlmm { > gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; > > + edp_reg_en: edp-reg-en-state { > + pins = "gpio25"; > + function = "gpio"; > + output-enable; > + }; > + > kybd_default: kybd-default-state { > disable-pins { > pins = "gpio102"; > -- > 2.37.3 >
On Fri, Dec 09, 2022 at 11:35:23AM +0100, Johan Hovold wrote: > On Wed, Dec 07, 2022 at 02:00:11PM -0800, Bjorn Andersson wrote: > > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > > > The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes > > and link it together with the backlight control. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > > --- > > > > Changes since v4: > > - None > > > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++++++++++++++++++++++- > > 1 file changed, 71 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > > index f09810e3d956..a7d2384cbbe8 100644 > > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > > @@ -20,7 +20,7 @@ aliases { > > serial0 = &qup2_uart17; > > }; > > > > - backlight { > > + backlight: backlight { > > compatible = "pwm-backlight"; > > pwms = <&pmc8280c_lpg 3 1000000>; > > enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; > > @@ -34,6 +34,22 @@ chosen { > > stdout-path = "serial0:115200n8"; > > }; > > > > + vreg_edp_3p3: regulator-edp-3p3 { > > + compatible = "regulator-fixed"; > > + > > + regulator-name = "VREG_EDP_3P3"; > > Please use the net name from the schematics here (i.e. "VCC3LCD"). > This is the name used in the CRD schematics. > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + > > + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&edp_reg_en>; > > + > > + regulator-boot-on; > > + }; > > + > > vreg_edp_bl: regulator-edp-bl { > > compatible = "regulator-fixed"; > > > > @@ -230,6 +246,54 @@ vreg_l9d: ldo9 { > > }; > > }; > > > > +&dispcc0 { > > + status = "okay"; > > +}; > > + > > +&mdss0 { > > + status = "okay"; > > +}; > > + > > +&mdss0_dp3 { > > + compatible = "qcom,sc8280xp-edp"; > > + status = "okay"; > > Please move the status property last (i.e. after data-lanes). > Sorry for missing that. > > + > > + data-lanes = <0 1 2 3>; > > + > > + aux-bus { > > + panel { > > + compatible = "edp-panel"; > > + power-supply = <&vreg_edp_3p3>; > > + > > + backlight = <&backlight>; > > + > > + ports { > > + port { > > + edp_panel_in: endpoint { > > + remote-endpoint = <&mdss0_dp3_out>; > > + }; > > + }; > > + }; > > + }; > > + }; > > + > > + ports { > > + port@1 { > > + reg = <1>; > > + mdss0_dp3_out: endpoint { > > + remote-endpoint = <&edp_panel_in>; > > + }; > > + }; > > + }; > > +}; > > + > > +&mdss0_dp3_phy { > > + status = "okay"; > > Same here. > Ditto. > > + > > + vdda-phy-supply = <&vreg_l6b>; > > + vdda-pll-supply = <&vreg_l3b>; > > +}; > > + > > &pcie2a { > > perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > > wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; > > @@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state { > > &tlmm { > > gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; > > > > + edp_reg_en: edp-reg-en-state { > > + pins = "gpio25"; > > + function = "gpio"; > > + output-enable; > > 'output-enable' is not valid for tlmm and causes the settings to be > rejected: > > sc8280xp-tlmm f100000.pinctrl: pin_config_group_set op failed for group 25 > reg-fixed-voltage regulator-edp-3p3: Error applying setting, reverse things back > Thanks for spotting that, it doesn't seem to be needed for the gpio-regulator driver anyways... Regards, Bjorn > > + }; > > + > > kybd_default: kybd-default-state { > > disable-pins { > > pins = "gpio102"; > > Johan
On Tue, Dec 13, 2022 at 07:10:14AM -0800, Bjorn Andersson wrote: > On Fri, Dec 09, 2022 at 11:35:23AM +0100, Johan Hovold wrote: > > > + edp_reg_en: edp-reg-en-state { > > > + pins = "gpio25"; > > > + function = "gpio"; > > > + output-enable; > > > > 'output-enable' is not valid for tlmm and causes the settings to be > > rejected: > > > > sc8280xp-tlmm f100000.pinctrl: pin_config_group_set op failed for group 25 > > reg-fixed-voltage regulator-edp-3p3: Error applying setting, reverse things back > > > > Thanks for spotting that, it doesn't seem to be needed for the gpio-regulator > driver anyways... I noticed that the firmware on both CRD and X13s sets the drive strength to 16 here. Should we specify that too (and disable the pull up) instead of relying on the firmware configuration? Johan
On 09/12/2022 01:31, Kuogee Hsieh wrote: > > On 12/7/2022 2:00 PM, Bjorn Andersson wrote: >> From: Bjorn Andersson <bjorn.andersson@linaro.org> >> >> The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 >> interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the >> necessary definitions and describe the DPU in the SC8280XP. >> >> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> >> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >> --- >> >> Changes since v4: >> - Fix highest_bank_bit, based on downstream >> - Add ubwc_swizzle >> - Use CTL_SC7280_MASK instead of listing the bits directly >> >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++ >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++ >> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >> drivers/gpu/drm/msm/msm_drv.h | 1 + >> 7 files changed, 243 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 2196e205efa5..0315fe68af2f 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -124,6 +124,19 @@ >> BIT(MDP_AD4_0_INTR) | \ >> BIT(MDP_AD4_1_INTR)) >> +#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >> + BIT(MDP_SSPP_TOP0_INTR2) | \ >> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >> + BIT(MDP_INTF0_7xxx_INTR) | \ >> + BIT(MDP_INTF1_7xxx_INTR) | \ >> + BIT(MDP_INTF2_7xxx_INTR) | \ >> + BIT(MDP_INTF3_7xxx_INTR) | \ >> + BIT(MDP_INTF4_7xxx_INTR) | \ >> + BIT(MDP_INTF5_7xxx_INTR) | \ >> + BIT(MDP_INTF6_7xxx_INTR) | \ >> + BIT(MDP_INTF7_7xxx_INTR) | \ >> + BIT(MDP_INTF8_7xxx_INTR)) >> + >> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >> BIT(DPU_WB_UBWC) | \ >> BIT(DPU_WB_YUV_CONFIG) | \ >> @@ -365,6 +378,20 @@ static const struct dpu_caps sc8180x_dpu_caps = { >> .max_vdeci_exp = MAX_VERT_DECIMATION, >> }; >> +static const struct dpu_caps sc8280xp_dpu_caps = { >> + .max_mixer_width = 2560, >> + .max_mixer_blendstages = 11, >> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, >> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >> + .ubwc_version = DPU_HW_UBWC_VER_40, >> + .has_src_split = true, >> + .has_dim_layer = true, >> + .has_idle_pc = true, >> + .has_3d_merge = true, >> + .max_linewidth = 5120, >> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> +}; >> + >> static const struct dpu_caps sm8250_dpu_caps = { >> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> .max_mixer_blendstages = 0xb, >> @@ -545,6 +572,25 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { >> }, >> }; >> +static const struct dpu_mdp_cfg sc8280xp_mdp[] = { >> + { >> + .name = "top_0", .id = MDP_TOP, >> + .base = 0x0, .len = 0x494, >> + .features = 0, >> + .highest_bank_bit = 2, >> + .ubwc_swizzle = 6, >> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0}, >> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0}, >> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0}, >> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, >> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, >> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, >> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = >> 8}, >> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = >> 8}, >> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = >> 20}, >> + }, >> +}; >> + >> static const struct dpu_mdp_cfg qcm2290_mdp[] = { >> { >> .name = "top_0", .id = MDP_TOP, >> @@ -648,6 +694,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { >> }, >> }; >> +static const struct dpu_ctl_cfg sc8280xp_ctl[] = { >> + { >> + .name = "ctl_0", .id = CTL_0, >> + .base = 0x15000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), >> + }, >> + { >> + .name = "ctl_1", .id = CTL_1, >> + .base = 0x16000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), >> + }, >> + { >> + .name = "ctl_2", .id = CTL_2, >> + .base = 0x17000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), >> + }, >> + { >> + .name = "ctl_3", .id = CTL_3, >> + .base = 0x18000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), >> + }, >> + { >> + .name = "ctl_4", .id = CTL_4, >> + .base = 0x19000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), >> + }, >> + { >> + .name = "ctl_5", .id = CTL_5, >> + .base = 0x1a000, .len = 0x204, >> + .features = CTL_SC7280_MASK, >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), >> + }, >> +}; >> + >> static const struct dpu_ctl_cfg sm8150_ctl[] = { >> { >> .name = "ctl_0", .id = CTL_0, >> @@ -926,6 +1011,33 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { >> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), >> }; >> +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = >> + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); >> +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 = >> + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); >> +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 = >> + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); >> +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 = >> + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); >> + >> +static const struct dpu_sspp_cfg sc8280xp_sspp[] = { >> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, >> + sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), >> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, >> + sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), >> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, >> + sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), >> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, >> + sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), >> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, >> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), >> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, >> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), >> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, >> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), >> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, >> + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), >> +}; >> #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ >> { \ >> @@ -1034,6 +1146,17 @@ static const struct dpu_lm_cfg sc7180_lm[] = { >> &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), >> }; >> +/* SC8280XP */ >> + >> +static const struct dpu_lm_cfg sc8280xp_lm[] = { >> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_0, LM_1, DSPP_0), >> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_1, LM_0, DSPP_1), >> + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_2, LM_3, DSPP_2), >> + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_3, LM_2, DSPP_3), >> + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_4, LM_5, 0), >> + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, >> PINGPONG_5, LM_4, 0), >> +}; >> + >> /* SM8150 */ >> static const struct dpu_lm_cfg sm8150_lm[] = { >> @@ -1192,6 +1315,21 @@ static struct dpu_pingpong_cfg sc7180_pp[] = { >> PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, >> sdm845_pp_sblk_te, -1, -1), >> }; >> +static struct dpu_pingpong_cfg sc8280xp_pp[] = { >> + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), >> + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), >> + PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), >> + PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), >> + PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), >> + PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, >> sdm845_pp_sblk_te, >> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), >> +}; >> + >> static const struct dpu_pingpong_cfg sm8150_pp[] = { >> PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, >> sdm845_pp_sblk_te, >> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), >> @@ -1243,6 +1381,12 @@ static const struct dpu_merge_3d_cfg >> sm8150_merge_3d[] = { >> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), >> }; >> +static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { >> + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), >> + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), >> + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), >> +}; >> + >> /************************************************************* >> * DSC sub blocks config >> *************************************************************/ >> @@ -1317,6 +1461,19 @@ static const struct dpu_intf_cfg sc8180x_intf[] >> = { >> INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, >> MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), >> }; >> +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for >> now */ >> +static const struct dpu_intf_cfg sc8280xp_intf[] = { >> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, >> 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >> + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >> + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), >> + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, >> MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), >> + INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, >> 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21), >> + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, >> 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), >> + INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, >> 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17), >> + INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, >> MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19), >> + INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, >> MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13), >> +}; >> + >> static const struct dpu_intf_cfg qcm2290_intf[] = { >> INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), >> INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, >> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >> @@ -1419,6 +1576,14 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { >> }, >> }; >> +static const struct dpu_reg_dma_cfg sc8280xp_regdma = { >> + .base = 0x0, >> + .version = 0x00020000, >> + .trigger_sel_off = 0x119c, >> + .xin_id = 7, >> + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, >> +}; >> + >> static const struct dpu_reg_dma_cfg sdm845_regdma = { >> .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c >> }; >> @@ -1690,6 +1855,33 @@ static const struct dpu_perf_cfg >> sc8180x_perf_data = { >> .min_llcc_ib = 800000, >> .min_dram_ib = 800000, >> .danger_lut_tbl = {0xf, 0xffff, 0x0}, >> + .qos_lut_tbl = { >> + {.nentry = ARRAY_SIZE(sc7180_qos_linear), >> + .entries = sc7180_qos_linear >> + }, >> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), >> + .entries = sc7180_qos_macrotile >> + }, >> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), >> + .entries = sc7180_qos_nrt >> + }, >> + /* TODO: macrotile-qseed is different from macrotile */ >> + }, >> + .cdp_cfg = { >> + {.rd_enable = 1, .wr_enable = 1}, >> + {.rd_enable = 1, .wr_enable = 0} >> + }, >> + .clk_inefficiency_factor = 105, >> + .bw_inefficiency_factor = 120, >> +}; >> + >> +static const struct dpu_perf_cfg sc8280xp_perf_data = { >> + .max_bw_low = 13600000, >> + .max_bw_high = 18200000, >> + .min_core_ib = 2500000, >> + .min_llcc_ib = 0, >> + .min_dram_ib = 800000, >> + .danger_lut_tbl = {0xf, 0xffff, 0x0}, >> .qos_lut_tbl = { >> {.nentry = ARRAY_SIZE(sc8180x_qos_linear), >> .entries = sc8180x_qos_linear It seems this chunk got wrong somehow during rebases. It changes sc8180x to use sc7280 QoS settings. I'll update it to keep the sc8180x data intact while applying. >> @@ -1937,6 +2129,30 @@ static const struct dpu_mdss_cfg >> sc8180x_dpu_cfg = { >> .mdss_irqs = IRQ_SC8180X_MASK, >> }; >> +static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = { >> + .caps = &sc8280xp_dpu_caps, >> + .mdp_count = ARRAY_SIZE(sc8280xp_mdp), >> + .mdp = sc8280xp_mdp, >> + .ctl_count = ARRAY_SIZE(sc8280xp_ctl), >> + .ctl = sc8280xp_ctl, >> + .sspp_count = ARRAY_SIZE(sc8280xp_sspp), >> + .sspp = sc8280xp_sspp, >> + .mixer_count = ARRAY_SIZE(sc8280xp_lm), >> + .mixer = sc8280xp_lm, >> + .dspp_count = ARRAY_SIZE(sm8150_dspp), >> + .dspp = sm8150_dspp, >> + .pingpong_count = ARRAY_SIZE(sc8280xp_pp), >> + .pingpong = sc8280xp_pp, >> + .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), >> + .merge_3d = sc8280xp_merge_3d, >> + .intf_count = ARRAY_SIZE(sc8280xp_intf), >> + .intf = sc8280xp_intf, >> + .vbif_count = ARRAY_SIZE(sdm845_vbif), >> + .vbif = sdm845_vbif, >> + .perf = &sc8280xp_perf_data, >> + .mdss_irqs = IRQ_SC8280XP_MASK, >> +}; >> + >> static const struct dpu_mdss_cfg sm8250_dpu_cfg = { >> .caps = &sm8250_dpu_caps, >> .mdp_count = ARRAY_SIZE(sm8250_mdp), >> @@ -2024,6 +2240,7 @@ static const struct dpu_mdss_hw_cfg_handler >> cfg_handler[] = { >> { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, >> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, >> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, >> + { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg}, >> }; >> const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 3b645d5aa9aa..6897b35c18fa 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -47,6 +47,7 @@ >> #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ >> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ >> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ >> +#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ >> #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), >> DPU_HW_VER_170) >> #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), >> DPU_HW_VER_300) >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c >> index cf1b6d84c18a..27d74c4d8a98 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c >> @@ -35,6 +35,9 @@ >> #define MDP_INTF_3_OFF_REV_7xxx 0x37000 >> #define MDP_INTF_4_OFF_REV_7xxx 0x38000 >> #define MDP_INTF_5_OFF_REV_7xxx 0x39000 >> +#define MDP_INTF_6_OFF_REV_7xxx 0x3a000 >> +#define MDP_INTF_7_OFF_REV_7xxx 0x3b000 >> +#define MDP_INTF_8_OFF_REV_7xxx 0x3c000 >> /** >> * struct dpu_intr_reg - array of DPU register sets >> @@ -139,6 +142,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = { >> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, >> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS >> }, >> + [MDP_INTF6_7xxx_INTR] = { >> + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR, >> + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN, >> + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS >> + }, >> + [MDP_INTF7_7xxx_INTR] = { >> + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR, >> + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN, >> + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS >> + }, >> + [MDP_INTF8_7xxx_INTR] = { >> + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR, >> + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN, >> + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS >> + }, >> }; >> #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h >> index 46443955443c..425465011c80 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h >> @@ -31,6 +31,9 @@ enum dpu_hw_intr_reg { >> MDP_INTF3_7xxx_INTR, >> MDP_INTF4_7xxx_INTR, >> MDP_INTF5_7xxx_INTR, >> + MDP_INTF6_7xxx_INTR, >> + MDP_INTF7_7xxx_INTR, >> + MDP_INTF8_7xxx_INTR, >> MDP_INTR_MAX, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h >> index d3b0ed0a9c6c..d595096a4b1f 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h >> @@ -214,6 +214,8 @@ enum dpu_intf { >> INTF_4, >> INTF_5, >> INTF_6, >> + INTF_7, >> + INTF_8, >> INTF_MAX >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index b71199511a52..30f894864cca 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -1292,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = { >> { .compatible = "qcom,sc7180-dpu", }, >> { .compatible = "qcom,sc7280-dpu", }, >> { .compatible = "qcom,sc8180x-dpu", }, >> + { .compatible = "qcom,sc8280xp-dpu", }, >> { .compatible = "qcom,sm6115-dpu", }, >> { .compatible = "qcom,sm8150-dpu", }, >> { .compatible = "qcom,sm8250-dpu", }, >> diff --git a/drivers/gpu/drm/msm/msm_drv.h >> b/drivers/gpu/drm/msm/msm_drv.h >> index d4e0ef608950..b2789efd59e8 100644 >> --- a/drivers/gpu/drm/msm/msm_drv.h >> +++ b/drivers/gpu/drm/msm/msm_drv.h >> @@ -61,6 +61,7 @@ enum msm_dp_controller { >> MSM_DP_CONTROLLER_0, >> MSM_DP_CONTROLLER_1, >> MSM_DP_CONTROLLER_2, >> + MSM_DP_CONTROLLER_3, >> MSM_DP_CONTROLLER_COUNT, >> };
On Wed, 07 Dec 2022 14:00:00 -0800, Bjorn Andersson wrote: > This introduces support for the SC8280XP platform in the MDSS, DPU and > DP driver. It reworks the HDP handling in the DP driver to support > external HPD sources - such as the dp-connector, or USB Type-C altmode. > > It then introduces the display clock controllers, mdss, dpu and > displayport controllers and link everything together, for both the MDSS > instances on the platform, and lastly enables EDP on the compute > reference device and 6 of the MiniDP outputs on the automotive > development platform. > > [...] Applied, thanks! [01/12] dt-bindings: display/msm: Add binding for SC8280XP MDSS https://gitlab.freedesktop.org/lumag/msm/-/commit/9ae2a57bdf9a [02/12] drm/msm/dpu: Introduce SC8280XP https://gitlab.freedesktop.org/lumag/msm/-/commit/f0a1bdf64dd7 [03/12] drm/msm: Introduce SC8280XP MDSS https://gitlab.freedesktop.org/lumag/msm/-/commit/39bcdb416fb6 [04/12] dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles https://gitlab.freedesktop.org/lumag/msm/-/commit/b6f8c4debc00 [05/12] drm/msm/dp: Stop using DP id as index in desc https://gitlab.freedesktop.org/lumag/msm/-/commit/5d417b401146 [06/12] drm/msm/dp: Add DP and EDP compatibles for SC8280XP https://gitlab.freedesktop.org/lumag/msm/-/commit/5bd69fd16198 [07/12] drm/msm/dp: Add SDM845 DisplayPort instance https://gitlab.freedesktop.org/lumag/msm/-/commit/fa33f2aa9674 [08/12] drm/msm/dp: Rely on hpd_enable/disable callbacks https://gitlab.freedesktop.org/lumag/msm/-/commit/cd198caddea7 [09/12] drm/msm/dp: Implement hpd_notify() https://gitlab.freedesktop.org/lumag/msm/-/commit/542b37efc20e Best regards,
On 08/12/2022 00:00, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > Define the display clock controllers, the MDSS instances, the DP phys > and connect these together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > 1 file changed, 838 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 9f3132ac2857..c2f186495506 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -4,6 +4,7 @@ > * Copyright (c) 2022, Linaro Limited > */ > > +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interconnect/qcom,sc8280xp.h> > @@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 { > status = "disabled"; > }; > > + mdss1_dp0_phy: phy@8909a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x08909a00 0 0x19c>, > + <0 0x08909200 0 0xec>, > + <0 0x08909600 0 0xec>, > + <0 0x08909000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss1_dp1_phy: phy@890ca00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x0890ca00 0 0x19c>, > + <0 0x0890c200 0 0xec>, > + <0 0x0890c600 0 0xec>, > + <0 0x0890c000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > system-cache-controller@9200000 { > compatible = "qcom,sc8280xp-llcc"; > reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; > @@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a800000 { > }; > }; > > + mdss0: display-subsystem@ae00000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc0 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss0_mdp: display-controller@ae01000 { > + compatible = "qcom,sc8280xp-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <460000000>, > + <19200000>; > + > + operating-points-v2 = <&mdss0_mdp_opp_table>; > + power-domains = <&rpmhpd SC8280XP_MMCX>; > + > + interrupt-parent = <&mdss0>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@5 { > + reg = <5>; > + mdss0_intf5_out: endpoint { > + remote-endpoint = <&mdss0_dp3_in>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + mdss0_intf6_out: endpoint { > + remote-endpoint = <&mdss0_dp2_in>; > + }; > + }; > + }; This now fails with: arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000: ports: 'port@0' is a required property From schema: Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('ports' was unexpected) From schema: Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml We do not map reg ids to INTF indices. So, unless you plan to change that, could you please change these to port@0 / port@1 ? [skipped the rest]
On Wed, Jan 18, 2023 at 04:58:26AM +0200, Dmitry Baryshkov wrote: > On 08/12/2022 00:00, Bjorn Andersson wrote: > > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > > > Define the display clock controllers, the MDSS instances, the DP phys > > and connect these together. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > > --- > > > > Changes since v4: > > - None > > > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > > 1 file changed, 838 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > index 9f3132ac2857..c2f186495506 100644 > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > @@ -4,6 +4,7 @@ > > * Copyright (c) 2022, Linaro Limited > > */ > > +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> > > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> > > #include <dt-bindings/clock/qcom,rpmh.h> > > #include <dt-bindings/interconnect/qcom,sc8280xp.h> > > @@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 { > > status = "disabled"; > > }; > > + mdss1_dp0_phy: phy@8909a00 { > > + compatible = "qcom,sc8280xp-dp-phy"; > > + reg = <0 0x08909a00 0 0x19c>, > > + <0 0x08909200 0 0xec>, > > + <0 0x08909600 0 0xec>, > > + <0 0x08909000 0 0x1c8>; > > + > > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, > > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > > + clock-names = "aux", "cfg_ahb"; > > + > > + power-domains = <&rpmhpd SC8280XP_MX>; > > + > > + #clock-cells = <1>; > > + #phy-cells = <0>; > > + > > + status = "disabled"; > > + }; > > + > > + mdss1_dp1_phy: phy@890ca00 { > > + compatible = "qcom,sc8280xp-dp-phy"; > > + reg = <0 0x0890ca00 0 0x19c>, > > + <0 0x0890c200 0 0xec>, > > + <0 0x0890c600 0 0xec>, > > + <0 0x0890c000 0 0x1c8>; > > + > > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, > > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > > + clock-names = "aux", "cfg_ahb"; > > + > > + power-domains = <&rpmhpd SC8280XP_MX>; > > + > > + #clock-cells = <1>; > > + #phy-cells = <0>; > > + > > + status = "disabled"; > > + }; > > + > > system-cache-controller@9200000 { > > compatible = "qcom,sc8280xp-llcc"; > > reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; > > @@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a800000 { > > }; > > }; > > + mdss0: display-subsystem@ae00000 { > > + compatible = "qcom,sc8280xp-mdss"; > > + reg = <0 0x0ae00000 0 0x1000>; > > + reg-names = "mdss"; > > + > > + power-domains = <&dispcc0 MDSS_GDSC>; > > + > > + clocks = <&gcc GCC_DISP_AHB_CLK>, > > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; > > + clock-names = "iface", > > + "ahb", > > + "core"; > > + > > + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; > > + > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + > > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > > + interconnect-names = "mdp0-mem", "mdp1-mem"; > > + > > + iommus = <&apps_smmu 0x1000 0x402>; > > + > > + status = "disabled"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + mdss0_mdp: display-controller@ae01000 { > > + compatible = "qcom,sc8280xp-dpu"; > > + reg = <0 0x0ae01000 0 0x8f000>, > > + <0 0x0aeb0000 0 0x2008>; > > + reg-names = "mdp", "vbif"; > > + > > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > > + <&gcc GCC_DISP_SF_AXI_CLK>, > > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > > + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, > > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > > + clock-names = "bus", > > + "nrt_bus", > > + "iface", > > + "lut", > > + "core", > > + "vsync"; > > + > > + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > > + assigned-clock-rates = <460000000>, > > + <19200000>; > > + > > + operating-points-v2 = <&mdss0_mdp_opp_table>; > > + power-domains = <&rpmhpd SC8280XP_MMCX>; > > + > > + interrupt-parent = <&mdss0>; > > + interrupts = <0>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@5 { > > + reg = <5>; > > + mdss0_intf5_out: endpoint { > > + remote-endpoint = <&mdss0_dp3_in>; > > + }; > > + }; > > + > > + port@6 { > > + reg = <6>; > > + mdss0_intf6_out: endpoint { > > + remote-endpoint = <&mdss0_dp2_in>; > > + }; > > + }; > > + }; > > This now fails with: > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000: > ports: 'port@0' is a required property > From schema: > Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml > arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000: > Unevaluated properties are not allowed ('ports' was unexpected) > From schema: > Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml > > We do not map reg ids to INTF indices. So, unless you plan to change that, > could you please change these to port@0 / port@1 ? > Too bad, I liked the fact that I gave these numbers any form of meaning. I guess we can change it to just be an arbitrary index, and keep the intf-information in the label... Regards, Bjorn > [skipped the rest] > > -- > With best wishes > Dmitry >