| Message ID | 20221205163754.221139-1-robert.foss@linaro.org |
|---|---|
| Headers | show |
| Series | Enable Display for SM8350 | expand |
On 05/12/2022 17:37, Robert Foss wrote: > Add compatibility for SM8350 display subsystem, including > required entries in DPU hw catalog. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > 2 files changed, 197 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4dac90ee5b8a..ba26af73be53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -112,6 +112,15 @@ > BIT(MDP_INTF3_INTR) | \ > BIT(MDP_INTF4_INTR)) > > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8350_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 4096, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8450_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8350_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sm8450_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sm8350_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x1e8, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x1e8, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sm8450_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { > -1), > }; > > +static const struct dpu_pingpong_cfg sm8350_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + -1), > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > + -1), > +}; > + > static struct dpu_pingpong_cfg qcm2290_pp[] = { > PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > +}; > + > static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = { > DSC_BLK("dsc_3", DSC_3, 0x80c00), > }; > > +static struct dpu_dsc_cfg sm8350_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000), > + DSC_BLK("dsc_1", DSC_1, 0x81000), > + DSC_BLK("dsc_2", DSC_2, 0x82000), > +}; > + > /************************************************************* > * INTF sub blocks config > *************************************************************/ > @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = { > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > }; > > +static const struct dpu_intf_cfg sm8350_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > }; > > +static const struct dpu_reg_dma_cfg sm8350_regdma = { > + .base = 0x400, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > static const struct dpu_reg_dma_cfg sm8450_regdma = { > .base = 0x0, > .version = 0x00020000, > @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = { > .bw_inefficiency_factor = 120, > }; > > +static const struct dpu_perf_cfg sm8350_perf_data = { > + .max_bw_low = 11800000, > + .max_bw_high = 15500000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .min_prefill_lines = 40, > + /* FIXME: lut tables */ > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg qcm2290_perf_data = { > .max_bw_low = 2700000, > .max_bw_high = 2700000, > @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sm8350_dpu_cfg = { > + .caps = &sm8350_dpu_caps, > + .mdp_count = ARRAY_SIZE(sm8350_mdp), > + .mdp = sm8350_mdp, > + .ctl_count = ARRAY_SIZE(sm8350_ctl), > + .ctl = sm8350_ctl, > + .sspp_count = ARRAY_SIZE(sm8250_sspp), > + .sspp = sm8250_sspp, > + .mixer_count = ARRAY_SIZE(sm8150_lm), > + .mixer = sm8150_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sm8350_pp), > + .pingpong = sm8350_pp, > + .dsc_count = ARRAY_SIZE(sm8350_dsc), > + .dsc = sm8350_dsc, > + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), > + .merge_3d = sm8350_merge_3d, > + .intf_count = ARRAY_SIZE(sm8350_intf), > + .intf = sm8350_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sm8250_regdma, > + .perf = &sm8350_perf_data, > + .mdss_irqs = IRQ_SM8350_MASK, > +}; > + > static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > .caps = &sm8450_dpu_caps, > .mdp_count = ARRAY_SIZE(sm8450_mdp), > @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 664c4876f44a..5335123a0289 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -45,6 +45,7 @@ > #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ >
On 05/12/2022 18:37, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++- > 1 file changed, 195 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..fb1c616c5e89 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { display-sybsystem@ I also had this issue in sm8450.dtsi (and I'm going to fix it in the next revision). > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { The mdp (dpu?) opp table belongs to the display-controller node. > + compatible = "operating-points-v2"; > + > + /* TODO: opp-200000000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + I have been changing the dsi's opp table, not this one. > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { And this table should go to dsi node. > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&dsi0_phy 0>, <&dsi0_phy 1>, > + <0>, <0>, Let's probably add both DSI controllers and DSI PHYs. It's fine if you can not verify the second one for real. > <0>, > <0>; > clock-names = "bi_tcxo", > @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > > power-domains = <&rpmhpd SM8350_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; As it's not a turbo level anymore, can we drop it completely? > }; > > adsp: remoteproc@17300000 {
On 05/12/2022 17:37, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > subsystem unit used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index a2264fb517a1..39746b972cdd 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > /* UBWC_2_0 */ > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > break; > + case DPU_HW_VER_700: > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > + break; > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8350-mdss" }, > { .compatible = "qcom,sm8450-mdss" }, > {} > };
On 05/12/2022 18:37, Robert Foss wrote: > Enable the display subsystem and the dsi0 output for > the sm8350-hdk board. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > index e6deb08c6da0..39462c659c58 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > @@ -213,10 +213,32 @@ &cdsp { > firmware-name = "qcom/sm8350/cdsp.mbn"; > }; > > +&dispcc { > + status = "okay"; > +}; > + > +&dsi0 { Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and PHY, as it allows us to group them nicely. WDYT? > + vdda-supply = <&vreg_l6b_1p2>; > + status = "okay"; > +}; > + > +&dsi0_phy { > + vdds-supply = <&vreg_l5b_0p88>; > + status = "okay"; > +}; > + > &gpi_dma1 { > status = "okay"; > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_mdp { > + status = "okay"; > +}; > + > &mpss { > status = "okay"; > firmware-name = "qcom/sm8350/modem.mbn";
On 05/12/2022 17:37, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++- > 1 file changed, 195 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..fb1c616c5e89 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { Based on bindings: display-subsystem > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* TODO: opp-200000000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { node name: opp-table > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + Best regards, Krzysztof
On 05/12/2022 17:37, Robert Foss wrote: > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. > > In order to toggle the board to enable the HDMI output, > switch #7 & #8 on the rightmost multi-switch package have > to be toggled to On. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Thank you for your patch. There is something to discuss/improve. > + > &slpi { > status = "okay"; > firmware-name = "qcom/sm8350/slpi.mbn"; > @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { > drive-strength = <2>; > output-low; > }; > + > + lt9611_state: lt9611-state { > + lt9611_rst_pin { No underscores in node names. > + pins = "gpio48"; > + function = "normal"; > + > + output-high; > + input-disable; > + }; > + > + lt9611_irq_pin { Ditto > + pins = "gpio50"; > + function = "gpio"; > + bias-disable; > + }; > + }; > }; Best regards, Krzysztof
On 05/12/2022 17:37, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++- > 1 file changed, 195 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..fb1c616c5e89 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { With the 8280 patchset [1], it was decided that mdss nodes should now have a mdss_ prefix in their labels, to keep them near each other when referencing them in device DTSes. > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* TODO: opp-200000000 should work with /* * TODO: and the wrapping looks rather weird.. or is that my email client? Other than that, lgtm! Konrad [1] https://lore.kernel.org/linux-arm-msm/20221130200739.ube7hvobythkbhuy@builder.lan/T/#m93e15b290b40c2d2c2ec6f639135ffa38882d0b2 > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&dsi0_phy 0>, <&dsi0_phy 1>, > + <0>, <0>, > <0>, > <0>; > clock-names = "bi_tcxo", > @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > > power-domains = <&rpmhpd SM8350_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > }; > > adsp: remoteproc@17300000 {
Hi Robert, On 5.12.22 18:37, Robert Foss wrote: > Use two interconnect cells in order to optionally > support a path tag. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 805d53d91952..434f8e8b12c1 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 { > config_noc: interconnect@1500000 { > compatible = "qcom,sm8350-config-noc"; > reg = <0 0x01500000 0 0xa580>; > - #interconnect-cells = <1>; > + #interconnect-cells = <2>; > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > mc_virt: interconnect@1580000 { > compatible = "qcom,sm8350-mc-virt"; > reg = <0 0x01580000 0 0x1000>; > - #interconnect-cells = <1>; > + #interconnect-cells = <2>; > qcom,bcm-voters = <&apps_bcm_voter>; > }; [..] > @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 { > clocks = <&rpmhcc RPMH_IPA_CLK>; > clock-names = "core"; > > - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, > - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; > + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; > interconnect-names = "memory", > "config"; > > @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 { > <&rpmhpd SM8350_MSS>; > power-domain-names = "cx", "mss"; > > - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; > + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>; The second cell for the first endpoint is missing, so this should be: interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; Thanks, Georgi > > memory-region = <&pil_modem_mem>; > > @@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 { > <&rpmhpd SM8350_MXC>; > power-domain-names = "cx", "mxc"; > > - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; > + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; > > memory-region = <&pil_cdsp_mem>; > > @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 { > dc_noc: interconnect@90c0000 { > compatible = "qcom,sm8350-dc-noc"; > reg = <0 0x090c0000 0 0x4200>; > - #interconnect-cells = <1>; > + #interconnect-cells = <2>; > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > gem_noc: interconnect@9100000 { > compatible = "qcom,sm8350-gem-noc"; > reg = <0 0x09100000 0 0xb4000>; > - #interconnect-cells = <1>; > + #interconnect-cells = <2>; > qcom,bcm-voters = <&apps_bcm_voter>; > }; >
On 05/12/2022 18:37, Robert Foss wrote: > Add compatibility for SM8350 display subsystem, including > required entries in DPU hw catalog. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Minor nit below. > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > 2 files changed, 197 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4dac90ee5b8a..ba26af73be53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -112,6 +112,15 @@ > BIT(MDP_INTF3_INTR) | \ > BIT(MDP_INTF4_INTR)) > > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8350_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 4096, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8450_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8350_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ Missing ubwc_swizzle. I'll probably fix it as a followup or when applying the patch. > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > + >
On 05/12/2022 18:37, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-dpu", for the display processing unit > used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 12/5/2022 8:37 AM, Robert Foss wrote: > Add compatibility for SM8350 display subsystem, including > required entries in DPU hw catalog. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > 2 files changed, 197 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4dac90ee5b8a..ba26af73be53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -112,6 +112,15 @@ > BIT(MDP_INTF3_INTR) | \ > BIT(MDP_INTF4_INTR)) > > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8350_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 4096, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8450_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8350_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sm8450_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sm8350_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x1e8, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x1e8, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x1e8, > + .features = CTL_SC7280_MASK, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sm8450_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { > -1), > }; > > +static const struct dpu_pingpong_cfg sm8350_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + -1), > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > + -1), > +}; > + > static struct dpu_pingpong_cfg qcm2290_pp[] = { > PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > +}; > + > static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = { > DSC_BLK("dsc_3", DSC_3, 0x80c00), > }; > > +static struct dpu_dsc_cfg sm8350_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000), > + DSC_BLK("dsc_1", DSC_1, 0x81000), > + DSC_BLK("dsc_2", DSC_2, 0x82000), > +}; I think this was copied over from sm8250, but this is not right. sm8350 has only 2 DSC blocks not 3. So "dsc_2" is not there. Thats a change from sm8250. Please fix this. > + > /************************************************************* > * INTF sub blocks config > *************************************************************/ > @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = { > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > }; > > +static const struct dpu_intf_cfg sm8350_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > }; > > +static const struct dpu_reg_dma_cfg sm8350_regdma = { > + .base = 0x400, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > static const struct dpu_reg_dma_cfg sm8450_regdma = { > .base = 0x0, > .version = 0x00020000, > @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = { > .bw_inefficiency_factor = 120, > }; > > +static const struct dpu_perf_cfg sm8350_perf_data = { > + .max_bw_low = 11800000, > + .max_bw_high = 15500000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .min_prefill_lines = 40, > + /* FIXME: lut tables */ > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg qcm2290_perf_data = { > .max_bw_low = 2700000, > .max_bw_high = 2700000, > @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sm8350_dpu_cfg = { > + .caps = &sm8350_dpu_caps, > + .mdp_count = ARRAY_SIZE(sm8350_mdp), > + .mdp = sm8350_mdp, > + .ctl_count = ARRAY_SIZE(sm8350_ctl), > + .ctl = sm8350_ctl, > + .sspp_count = ARRAY_SIZE(sm8250_sspp), > + .sspp = sm8250_sspp, > + .mixer_count = ARRAY_SIZE(sm8150_lm), > + .mixer = sm8150_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sm8350_pp), > + .pingpong = sm8350_pp, > + .dsc_count = ARRAY_SIZE(sm8350_dsc), > + .dsc = sm8350_dsc, > + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), > + .merge_3d = sm8350_merge_3d, > + .intf_count = ARRAY_SIZE(sm8350_intf), > + .intf = sm8350_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sm8250_regdma, > + .perf = &sm8350_perf_data, > + .mdss_irqs = IRQ_SM8350_MASK, > +}; > + > static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > .caps = &sm8450_dpu_caps, > .mdp_count = ARRAY_SIZE(sm8450_mdp), > @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 664c4876f44a..5335123a0289 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -45,6 +45,7 @@ > #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ >
On 12/5/2022 8:37 AM, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-dpu", for the display processing unit > used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 9827914dc096..6048bfae0824 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc8180x-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > + { .compatible = "qcom,sm8350-dpu", }, > { .compatible = "qcom,sm8450-dpu", }, > {} > };
On 05/12/2022 18:37, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > subsystem unit used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index a2264fb517a1..39746b972cdd 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > /* UBWC_2_0 */ > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > break; > + case DPU_HW_VER_700: > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > + break; Judging from the vendor kernel, the highest_rank_bit is 3, with usual todo for 2 for LP_DDR4. > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8350-mdss" }, > { .compatible = "qcom,sm8450-mdss" }, > {} > };
On Mon, 5 Dec 2022 at 17:44, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 05/12/2022 18:37, Robert Foss wrote: > > Enable the display subsystem and the dsi0 output for > > the sm8350-hdk board. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > > index e6deb08c6da0..39462c659c58 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > > @@ -213,10 +213,32 @@ &cdsp { > > firmware-name = "qcom/sm8350/cdsp.mbn"; > > }; > > > > +&dispcc { > > + status = "okay"; > > +}; > > + > > +&dsi0 { > > Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and > PHY, as it allows us to group them nicely. WDYT? Sounds quite reasonable, fixing it in dts/dtsi/binding. > > > + vdda-supply = <&vreg_l6b_1p2>; > > + status = "okay"; > > +}; > > + > > +&dsi0_phy { > > + vdds-supply = <&vreg_l5b_0p88>; > > + status = "okay"; > > +}; > > + > > &gpi_dma1 { > > status = "okay"; > > }; > > > > +&mdss { > > + status = "okay"; > > +}; > > + > > +&mdss_mdp { > > + status = "okay"; > > +}; > > + > > &mpss { > > status = "okay"; > > firmware-name = "qcom/sm8350/modem.mbn"; > > -- > With best wishes > Dmitry >
On Mon, 5 Dec 2022 at 20:19, Georgi Djakov <djakov@kernel.org> wrote: > > Hi Robert, > > On 5.12.22 18:37, Robert Foss wrote: > > Use two interconnect cells in order to optionally > > support a path tag. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > index 805d53d91952..434f8e8b12c1 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 { > > config_noc: interconnect@1500000 { > > compatible = "qcom,sm8350-config-noc"; > > reg = <0 0x01500000 0 0xa580>; > > - #interconnect-cells = <1>; > > + #interconnect-cells = <2>; > > qcom,bcm-voters = <&apps_bcm_voter>; > > }; > > > > mc_virt: interconnect@1580000 { > > compatible = "qcom,sm8350-mc-virt"; > > reg = <0 0x01580000 0 0x1000>; > > - #interconnect-cells = <1>; > > + #interconnect-cells = <2>; > > qcom,bcm-voters = <&apps_bcm_voter>; > > }; > [..] > > @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 { > > clocks = <&rpmhcc RPMH_IPA_CLK>; > > clock-names = "core"; > > > > - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, > > - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; > > + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, > > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; > > interconnect-names = "memory", > > "config"; > > > > @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 { > > <&rpmhpd SM8350_MSS>; > > power-domain-names = "cx", "mss"; > > > > - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; > > + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>; > > The second cell for the first endpoint is missing, so this should be: > interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; Nice catch, thanks! > > Thanks, > Georgi > > > > > memory-region = <&pil_modem_mem>; > > > > @@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 { > > <&rpmhpd SM8350_MXC>; > > power-domain-names = "cx", "mxc"; > > > > - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; > > + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; > > > > memory-region = <&pil_cdsp_mem>; > > > > @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 { > > dc_noc: interconnect@90c0000 { > > compatible = "qcom,sm8350-dc-noc"; > > reg = <0 0x090c0000 0 0x4200>; > > - #interconnect-cells = <1>; > > + #interconnect-cells = <2>; > > qcom,bcm-voters = <&apps_bcm_voter>; > > }; > > > > gem_noc: interconnect@9100000 { > > compatible = "qcom,sm8350-gem-noc"; > > reg = <0 0x09100000 0 0xb4000>; > > - #interconnect-cells = <1>; > > + #interconnect-cells = <2>; > > qcom,bcm-voters = <&apps_bcm_voter>; > > }; > > >
On Thu, 8 Dec 2022 at 00:50, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 05/12/2022 18:37, Robert Foss wrote: > > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > > subsystem unit used on Qualcomm SM8350 platform. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > > index a2264fb517a1..39746b972cdd 100644 > > --- a/drivers/gpu/drm/msm/msm_mdss.c > > +++ b/drivers/gpu/drm/msm/msm_mdss.c > > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > > /* UBWC_2_0 */ > > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > > break; > > + case DPU_HW_VER_700: > > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > > + break; > > Judging from the vendor kernel, the highest_rank_bit is 3, with usual > todo for 2 for LP_DDR4. Thanks! Will fix. > > > case DPU_HW_VER_720: > > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > > break; > > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > > { .compatible = "qcom,sc8180x-mdss" }, > > { .compatible = "qcom,sm8150-mdss" }, > > { .compatible = "qcom,sm8250-mdss" }, > > + { .compatible = "qcom,sm8350-mdss" }, > > { .compatible = "qcom,sm8450-mdss" }, > > {} > > }; > > -- > With best wishes > Dmitry >
On Mon, 5 Dec 2022 at 17:47, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/12/2022 17:37, Robert Foss wrote: > > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. > > > > In order to toggle the board to enable the HDMI output, > > switch #7 & #8 on the rightmost multi-switch package have > > to be toggled to On. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Thank you for your patch. There is something to discuss/improve. > > > + > > &slpi { > > status = "okay"; > > firmware-name = "qcom/sm8350/slpi.mbn"; > > @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { > > drive-strength = <2>; > > output-low; > > }; > > + > > + lt9611_state: lt9611-state { > > + lt9611_rst_pin { > > No underscores in node names. Ack > > > + pins = "gpio48"; > > + function = "normal"; > > + > > + output-high; > > + input-disable; > > + }; > > + > > + lt9611_irq_pin { > > Ditto Ack > > > + pins = "gpio50"; > > + function = "gpio"; > > + bias-disable; > > + }; > > + }; > > }; > > Best regards, > Krzysztof >
On Thu, 8 Dec 2022 at 00:42, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > > > On 12/5/2022 8:37 AM, Robert Foss wrote: > > Add compatibility for SM8350 display subsystem, including > > required entries in DPU hw catalog. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > > 2 files changed, 197 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > index 4dac90ee5b8a..ba26af73be53 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > @@ -112,6 +112,15 @@ > > BIT(MDP_INTF3_INTR) | \ > > BIT(MDP_INTF4_INTR)) > > > > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > > + BIT(MDP_SSPP_TOP0_INTR2) | \ > > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > > + BIT(MDP_INTF0_7xxx_INTR) | \ > > + BIT(MDP_INTF1_7xxx_INTR) | \ > > + BIT(MDP_INTF2_7xxx_INTR) | \ > > + BIT(MDP_INTF3_7xxx_INTR) | \ > > + 0) > > + > > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > > BIT(MDP_SSPP_TOP0_INTR2) | \ > > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > > }; > > > > +static const struct dpu_caps sm8350_dpu_caps = { > > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > > + .max_mixer_blendstages = 0xb, > > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > > + .ubwc_version = DPU_HW_UBWC_VER_40, > > + .has_src_split = true, > > + .has_dim_layer = true, > > + .has_idle_pc = true, > > + .has_3d_merge = true, > > + .max_linewidth = 4096, > > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > > +}; > > + > > static const struct dpu_caps sm8450_dpu_caps = { > > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > > .max_mixer_blendstages = 0xb, > > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > > }, > > }; > > > > +static const struct dpu_mdp_cfg sm8350_mdp[] = { > > + { > > + .name = "top_0", .id = MDP_TOP, > > + .base = 0x0, .len = 0x494, > > + .features = 0, > > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > > + .reg_off = 0x2ac, .bit_off = 0}, > > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > > + .reg_off = 0x2b4, .bit_off = 0}, > > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > > + .reg_off = 0x2bc, .bit_off = 0}, > > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > > + .reg_off = 0x2c4, .bit_off = 0}, > > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > > + .reg_off = 0x2ac, .bit_off = 8}, > > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > > + .reg_off = 0x2b4, .bit_off = 8}, > > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > > + .reg_off = 0x2bc, .bit_off = 8}, > > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > > + .reg_off = 0x2c4, .bit_off = 8}, > > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > > + .reg_off = 0x2bc, .bit_off = 20}, > > + }, > > +}; > > + > > static const struct dpu_mdp_cfg sm8450_mdp[] = { > > { > > .name = "top_0", .id = MDP_TOP, > > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > > }, > > }; > > > > +static const struct dpu_ctl_cfg sm8350_ctl[] = { > > + { > > + .name = "ctl_0", .id = CTL_0, > > + .base = 0x15000, .len = 0x1e8, > > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > > + }, > > + { > > + .name = "ctl_1", .id = CTL_1, > > + .base = 0x16000, .len = 0x1e8, > > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > > + }, > > + { > > + .name = "ctl_2", .id = CTL_2, > > + .base = 0x17000, .len = 0x1e8, > > + .features = CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > > + }, > > + { > > + .name = "ctl_3", .id = CTL_3, > > + .base = 0x18000, .len = 0x1e8, > > + .features = CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > > + }, > > + { > > + .name = "ctl_4", .id = CTL_4, > > + .base = 0x19000, .len = 0x1e8, > > + .features = CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > > + }, > > + { > > + .name = "ctl_5", .id = CTL_5, > > + .base = 0x1a000, .len = 0x1e8, > > + .features = CTL_SC7280_MASK, > > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > > + }, > > +}; > > + > > static const struct dpu_ctl_cfg sm8450_ctl[] = { > > { > > .name = "ctl_0", .id = CTL_0, > > @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { > > -1), > > }; > > > > +static const struct dpu_pingpong_cfg sm8350_pp[] = { > > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > > + -1), > > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > > + -1), > > +}; > > + > > static struct dpu_pingpong_cfg qcm2290_pp[] = { > > PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, > > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > > @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > > }; > > > > +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { > > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > > +}; > > + > > static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > > MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > > MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > > @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = { > > DSC_BLK("dsc_3", DSC_3, 0x80c00), > > }; > > > > +static struct dpu_dsc_cfg sm8350_dsc[] = { > > + DSC_BLK("dsc_0", DSC_0, 0x80000), > > + DSC_BLK("dsc_1", DSC_1, 0x81000), > > + DSC_BLK("dsc_2", DSC_2, 0x82000), > > +}; > > I think this was copied over from sm8250, but this is not right. > > sm8350 has only 2 DSC blocks not 3. So "dsc_2" is not there. > > Thats a change from sm8250. > > Please fix this. Ack > > > + > > /************************************************************* > > * INTF sub blocks config > > *************************************************************/ > > @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = { > > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > > }; > > > > +static const struct dpu_intf_cfg sm8350_intf[] = { > > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > > +}; > > + > > static const struct dpu_intf_cfg sc8180x_intf[] = { > > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > > @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > > }; > > > > +static const struct dpu_reg_dma_cfg sm8350_regdma = { > > + .base = 0x400, > > + .version = 0x00020000, > > + .trigger_sel_off = 0x119c, > > + .xin_id = 7, > > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > > +}; > > + > > static const struct dpu_reg_dma_cfg sm8450_regdma = { > > .base = 0x0, > > .version = 0x00020000, > > @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = { > > .bw_inefficiency_factor = 120, > > }; > > > > +static const struct dpu_perf_cfg sm8350_perf_data = { > > + .max_bw_low = 11800000, > > + .max_bw_high = 15500000, > > + .min_core_ib = 2500000, > > + .min_llcc_ib = 0, > > + .min_dram_ib = 800000, > > + .min_prefill_lines = 40, > > + /* FIXME: lut tables */ > > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > > + .qos_lut_tbl = { > > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > > + .entries = sc7180_qos_linear > > + }, > > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > > + .entries = sc7180_qos_macrotile > > + }, > > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > > + .entries = sc7180_qos_nrt > > + }, > > + /* TODO: macrotile-qseed is different from macrotile */ > > + }, > > + .cdp_cfg = { > > + {.rd_enable = 1, .wr_enable = 1}, > > + {.rd_enable = 1, .wr_enable = 0} > > + }, > > + .clk_inefficiency_factor = 105, > > + .bw_inefficiency_factor = 120, > > +}; > > + > > static const struct dpu_perf_cfg qcm2290_perf_data = { > > .max_bw_low = 2700000, > > .max_bw_high = 2700000, > > @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > > .mdss_irqs = IRQ_SM8250_MASK, > > }; > > > > +static const struct dpu_mdss_cfg sm8350_dpu_cfg = { > > + .caps = &sm8350_dpu_caps, > > + .mdp_count = ARRAY_SIZE(sm8350_mdp), > > + .mdp = sm8350_mdp, > > + .ctl_count = ARRAY_SIZE(sm8350_ctl), > > + .ctl = sm8350_ctl, > > + .sspp_count = ARRAY_SIZE(sm8250_sspp), > > + .sspp = sm8250_sspp, > > + .mixer_count = ARRAY_SIZE(sm8150_lm), > > + .mixer = sm8150_lm, > > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > > + .dspp = sm8150_dspp, > > + .pingpong_count = ARRAY_SIZE(sm8350_pp), > > + .pingpong = sm8350_pp, > > + .dsc_count = ARRAY_SIZE(sm8350_dsc), > > + .dsc = sm8350_dsc, > > + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), > > + .merge_3d = sm8350_merge_3d, > > + .intf_count = ARRAY_SIZE(sm8350_intf), > > + .intf = sm8350_intf, > > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > > + .vbif = sdm845_vbif, > > + .reg_dma_count = 1, > > + .dma_cfg = &sm8250_regdma, > > + .perf = &sm8350_perf_data, > > + .mdss_irqs = IRQ_SM8350_MASK, > > +}; > > + > > static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > > .caps = &sm8450_dpu_caps, > > .mdp_count = ARRAY_SIZE(sm8450_mdp), > > @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > > { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, > > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > > + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg}, > > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > > { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > index 664c4876f44a..5335123a0289 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > @@ -45,6 +45,7 @@ > > #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ > > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > > +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ > > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > > #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ > >