| Message ID | 20221026032624.30871-1-quic_bjorande@quicinc.com |
|---|---|
| Headers | show |
| Series | drm/msm: Add SC8280XP support | expand |
On 26 October 2022 06:26:21 EEST, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: >From: Bjorn Andersson <bjorn.andersson@linaro.org> > >The DisplayPort controller's internal HPD interrupt handling is used for >cases where the HPD signal is connected to a GPIO which is pinmuxed into >the DisplayPort controller. > >Most of the logic for enabling and disabling the HPD-related interrupts >is conditioned on the presence of an EDP panel, but more generically >designs that has a downstream drm_bridge (next_bridge) could use this to >handle the HPD interrupts, instead of the internal mechanism. > >So replace the current is_edp-based guards with a check for the presence >of next_bridge. This does not sound correct. The next bridge might be a dummy bridge, not supporting the hpd. Please change this to use the enable_hpd()/disable_hpd() callbacks. This way the drm_bridge_connector framework will make sure to enable hpd handling for the bridge that is actually supposed to generate hpd events. > >Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> >Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> >--- > >Changes since v2: >- None
On Tue, Oct 25, 2022 at 08:26:24PM -0700, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SA8295P ADP has, among other interfaces, six MiniDP connectors which > are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. > > Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, > DP PHYs and link them all together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > &apps_rsc { > @@ -156,13 +240,169 @@ vreg_l7g: ldo7 { > > vreg_l8g: ldo8 { > regulator-name = "vreg_l8g"; > - regulator-min-microvolt = <880000>; > - regulator-max-microvolt = <880000>; > + regulator-min-microvolt = <912000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + regulator-allow-set-load; Did you really intend to allow set-load here? I'm guessing this wasn't the case, but otherwise you also need to specify the valid modes. > + }; > + > + vreg_l11g: ldo11 { > + regulator-name = "vreg_l11g"; > + regulator-min-microvolt = <912000>; > + regulator-max-microvolt = <912000>; > regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > }; > }; > }; > +&mdss0_dp2_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l8g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; Johan
On Tue, Oct 25, 2022 at 08:26:22PM -0700, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > Define the display clock controllers, the MDSS instances, the DP phys > and connect these together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v2: > - New patch on list > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > 1 file changed, 838 insertions(+) > + mdss0_mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + opp-600000000 { Super nit: missing newline between entries (I only noticed when rebasing the external DP support on top). > + opp-hz = /bits/ 64 <600000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + mdss1_mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; Ditto. > + }; > + }; Johan
On Wed, Oct 26, 2022 at 09:08:49AM +0300, Dmitry Baryshkov wrote: > > > On 26 October 2022 06:26:21 EEST, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > >From: Bjorn Andersson <bjorn.andersson@linaro.org> > > > >The DisplayPort controller's internal HPD interrupt handling is used for > >cases where the HPD signal is connected to a GPIO which is pinmuxed into > >the DisplayPort controller. > > > >Most of the logic for enabling and disabling the HPD-related interrupts > >is conditioned on the presence of an EDP panel, but more generically > >designs that has a downstream drm_bridge (next_bridge) could use this to > >handle the HPD interrupts, instead of the internal mechanism. > > > >So replace the current is_edp-based guards with a check for the presence > >of next_bridge. > > This does not sound correct. The next bridge might be a dummy bridge, > not supporting the hpd. I only considered checking for the Chrome case, where the output isn't modelled and we have to rely on the internal HPD logic. Checking that next_bridge is present and will deliver us hpd events sounds somewhat reasonable. But if I understand the code correctly, panel-edp isn't handing us hpd events - and we still don't want the internal HPD logic to trigger. So I presume I would need to check that this isn't a EDP controller and that we're going to get external HPD events? If so, clean you please give me some pointer on how to check if next_bridge will provide us with hpd signaling or not? PS. Which dummy bridge do you have in mind? > Please change this to use the enable_hpd()/disable_hpd() callbacks. > This way the drm_bridge_connector framework will make sure to enable > hpd handling for the bridge that is actually supposed to generate hpd > events. > The drm_bridge_connector_init() call in dp_drm_connector_init() does this for us already. Regards, Bjorn > > > > >Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > >Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > >--- > > > >Changes since v2: > >- None > > > -- > With best wishes > Dmitry
On Wed, Oct 26, 2022 at 01:50:15PM +0200, Johan Hovold wrote: > On Tue, Oct 25, 2022 at 08:26:24PM -0700, Bjorn Andersson wrote: > > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > > > The SA8295P ADP has, among other interfaces, six MiniDP connectors which > > are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. > > > > Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, > > DP PHYs and link them all together. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > > --- > > > &apps_rsc { > > @@ -156,13 +240,169 @@ vreg_l7g: ldo7 { > > > > vreg_l8g: ldo8 { > > regulator-name = "vreg_l8g"; > > - regulator-min-microvolt = <880000>; > > - regulator-max-microvolt = <880000>; > > + regulator-min-microvolt = <912000>; > > + regulator-max-microvolt = <912000>; > > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > > + regulator-allow-set-load; > > Did you really intend to allow set-load here? > > I'm guessing this wasn't the case, but otherwise you also need to > specify the valid modes. > I see no reason for keeping it at this point in time, will drop it. Thanks, Bjorn > > + }; > > + > > + vreg_l11g: ldo11 { > > + regulator-name = "vreg_l11g"; > > + regulator-min-microvolt = <912000>; > > + regulator-max-microvolt = <912000>; > > regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > > }; > > }; > > }; > > > +&mdss0_dp2_phy { > > + status = "okay"; > > + > > + vdda-phy-supply = <&vreg_l8g>; > > + vdda-pll-supply = <&vreg_l3g>; > > +}; > > Johan
On 26/10/2022 06:26, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 > interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the > necessary definitions and describe the DPU in the SC8280XP. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Change since v2: > - Dropped flag for hole in TOP > - Wrapped some lines to make checkpatch happier > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > drivers/gpu/drm/msm/msm_drv.h | 1 + > drivers/gpu/drm/msm/msm_mdss.c | 2 + > 8 files changed, 245 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 27f029fdc682..9964814be27a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -79,6 +79,8 @@ > > #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) > > +#define INTF_SC8280XP_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_DATA_HCTL_EN) This is equal to INTF_SC7280_MASK > + > #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -124,6 +126,19 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + BIT(MDP_INTF4_7xxx_INTR) | \ > + BIT(MDP_INTF5_7xxx_INTR) | \ > + BIT(MDP_INTF6_7xxx_INTR) | \ > + BIT(MDP_INTF7_7xxx_INTR) | \ > + BIT(MDP_INTF8_7xxx_INTR)) > + > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > @@ -350,6 +365,20 @@ static const struct dpu_caps sc8180x_dpu_caps = { > .max_vdeci_exp = MAX_VERT_DECIMATION, > }; > > +static const struct dpu_caps sc8280xp_dpu_caps = { > + .max_mixer_width = 2560, > + .max_mixer_blendstages = 11, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 5120, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8250_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -472,6 +501,24 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sc8280xp_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sm8250_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -620,6 +667,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sc8280xp_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), CTL_SC7280_MASK > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sm8150_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -849,6 +935,34 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { > sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = > + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 = > + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 = > + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 = > + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); > + > +static const struct dpu_sspp_cfg sc8280xp_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, It should be either DPU_SSPP_SCALER_QSEED4 in the sblks above or VIG_SM8250_MASK below. > + sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, > + sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, > + sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, > + sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = > _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = > @@ -996,6 +1110,15 @@ static const struct dpu_lm_cfg sc7180_lm[] = { > &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), > }; > > +static const struct dpu_lm_cfg sc8280xp_lm[] = { > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), Doesn't sc8280xp support DPU_MIXER_SOURCESPLIT? If it does, it should be MIXER_SDM845_MASK > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), > + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), > + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), > + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), > + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SC7180_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), > +}; > + > /* SM8150 */ > > static const struct dpu_lm_cfg sm8150_lm[] = { > @@ -1154,6 +1277,21 @@ static struct dpu_pingpong_cfg sc7180_pp[] = { > PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), > }; > > +static struct dpu_pingpong_cfg sc8280xp_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), > + PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), > + PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), > + PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), > + PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), > +}; > + > static const struct dpu_pingpong_cfg sm8150_pp[] = { > PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > @@ -1205,6 +1343,12 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { > PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), > }; > > +static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > +}; > + > /************************************************************* > * DSC sub blocks config > *************************************************************/ > @@ -1279,6 +1423,19 @@ static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > }; > > +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ > +static const struct dpu_intf_cfg sc8280xp_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > + INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 20, 21), > + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 22, 23), > + INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 16, 17), > + INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 18, 19), > + INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC8280XP_MASK, MDP_SSPP_TOP0_INTR, 12, 13), > +}; > + > static const struct dpu_intf_cfg qcm2290_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -1381,6 +1538,14 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { > }, > }; > > +static const struct dpu_reg_dma_cfg sc8280xp_regdma = { > + .base = 0x0, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > static const struct dpu_reg_dma_cfg sdm845_regdma = { > .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c > }; > @@ -1623,6 +1788,33 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { > .min_llcc_ib = 800000, > .min_dram_ib = 800000, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > +static const struct dpu_perf_cfg sc8280xp_perf_data = { > + .max_bw_low = 13600000, > + .max_bw_high = 18200000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .danger_lut_tbl = {0xf, 0xffff, 0x0}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc8180x_qos_linear), > .entries = sc8180x_qos_linear > @@ -1848,6 +2040,30 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { > .mdss_irqs = IRQ_SC8180X_MASK, > }; > > +static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = { > + .caps = &sc8280xp_dpu_caps, > + .mdp_count = ARRAY_SIZE(sc8280xp_mdp), > + .mdp = sc8280xp_mdp, > + .ctl_count = ARRAY_SIZE(sc8280xp_ctl), > + .ctl = sc8280xp_ctl, > + .sspp_count = ARRAY_SIZE(sc8280xp_sspp), > + .sspp = sc8280xp_sspp, > + .mixer_count = ARRAY_SIZE(sc8280xp_lm), > + .mixer = sc8280xp_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sc8280xp_pp), > + .pingpong = sc8280xp_pp, > + .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), > + .merge_3d = sc8280xp_merge_3d, > + .intf_count = ARRAY_SIZE(sc8280xp_intf), > + .intf = sc8280xp_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .perf = &sc8280xp_perf_data, > + .mdss_irqs = IRQ_SC8280XP_MASK, > +}; > + > static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .caps = &sm8250_dpu_caps, > .mdp_count = ARRAY_SIZE(sm8250_mdp), > @@ -1934,6 +2150,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg}, > }; > > const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 38aa38ab1568..c4c675c40a57 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -46,6 +46,7 @@ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > +#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ > > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) > #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index cf1b6d84c18a..27d74c4d8a98 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -35,6 +35,9 @@ > #define MDP_INTF_3_OFF_REV_7xxx 0x37000 > #define MDP_INTF_4_OFF_REV_7xxx 0x38000 > #define MDP_INTF_5_OFF_REV_7xxx 0x39000 > +#define MDP_INTF_6_OFF_REV_7xxx 0x3a000 > +#define MDP_INTF_7_OFF_REV_7xxx 0x3b000 > +#define MDP_INTF_8_OFF_REV_7xxx 0x3c000 > > /** > * struct dpu_intr_reg - array of DPU register sets > @@ -139,6 +142,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = { > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS > }, > + [MDP_INTF6_7xxx_INTR] = { > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > + [MDP_INTF7_7xxx_INTR] = { > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > + [MDP_INTF8_7xxx_INTR] = { > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR, > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN, > + MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS > + }, > }; > > #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > index 46443955443c..425465011c80 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > @@ -31,6 +31,9 @@ enum dpu_hw_intr_reg { > MDP_INTF3_7xxx_INTR, > MDP_INTF4_7xxx_INTR, > MDP_INTF5_7xxx_INTR, > + MDP_INTF6_7xxx_INTR, > + MDP_INTF7_7xxx_INTR, > + MDP_INTF8_7xxx_INTR, > MDP_INTR_MAX, > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index d3b0ed0a9c6c..d595096a4b1f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -214,6 +214,8 @@ enum dpu_intf { > INTF_4, > INTF_5, > INTF_6, > + INTF_7, > + INTF_8, > INTF_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 5e6e2626151e..db2e4bb4e208 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1304,6 +1304,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc7180-dpu", }, > { .compatible = "qcom,sc7280-dpu", }, > { .compatible = "qcom,sc8180x-dpu", }, > + { .compatible = "qcom,sc8280xp-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > {} > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index b2ea262296a4..2dd342e49de6 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -61,6 +61,7 @@ enum msm_dp_controller { > MSM_DP_CONTROLLER_0, > MSM_DP_CONTROLLER_1, > MSM_DP_CONTROLLER_2, > + MSM_DP_CONTROLLER_3, > MSM_DP_CONTROLLER_COUNT, > }; > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index e13c5c12b775..7c391fab6263 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -208,6 +208,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC); > break; > case DPU_HW_VER_600: > + case DPU_HW_VER_800: > /* TODO: 0x102e for LP_DDR4 */ > writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC); > writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); > @@ -445,6 +446,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc7180-mdss" }, > { .compatible = "qcom,sc7280-mdss" }, > { .compatible = "qcom,sc8180x-mdss" }, > + { .compatible = "qcom,sc8280xp-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > {} Please split mdss into the separate patch.
On 26/10/2022 06:26, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > In the SC8280XP platform there are two identical MDSS instances, each > with the same set of DisplayPort instances, at different addresses. > > By not relying on the index to define the instance id it's possible to > describe them both in the same table and hence have a single compatible. > > While at it, flatten the cfg/desc structure so that the match data is > just an array of descs. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > > Changes since v2: > - None > > drivers/gpu/drm/msm/dp/dp_display.c | 72 ++++++++++------------------- > 1 file changed, 25 insertions(+), 47 deletions(-)-- With best wishes Dmitry
On 10/25/2022 8:26 PM, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > Define the display clock controllers, the MDSS instances, the DP phys > and connect these together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v2: > - New patch on list > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > 1 file changed, 838 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index ed806a6e20f6..8526ed74b7be 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -4,6 +4,7 @@ > * Copyright (c) 2022, Linaro Limited > */ > > +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interconnect/qcom,sc8280xp.h> > @@ -1245,6 +1246,44 @@ usb_1_ssphy: usb3-phy@8903400 { > }; > }; > > + mdss1_dp0_phy: phy@8909a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x08909a00 0 0x19c>, > + <0 0x08909200 0 0xec>, > + <0 0x08909600 0 0xec>, > + <0 0x08909000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss1_dp1_phy: phy@890ca00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x0890ca00 0 0x19c>, > + <0 0x0890c200 0 0xec>, > + <0 0x0890c600 0 0xec>, > + <0 0x0890c000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > system-cache-controller@9200000 { > compatible = "qcom,sc8280xp-llcc"; > reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; > @@ -1360,6 +1399,326 @@ usb_1_dwc3: usb@a800000 { > }; > }; > > + mdss0: display-subsystem@ae00000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc0 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss0_mdp: display-controller@ae01000 { > + compatible = "qcom,sc8280xp-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <460000000>, > + <19200000>; > + > + operating-points-v2 = <&mdss0_mdp_opp_table>; > + power-domains = <&rpmhpd SC8280XP_MMCX>; > + > + interrupt-parent = <&mdss0>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@5 { > + reg = <5>; > + mdss0_intf5_out: endpoint { > + remote-endpoint = <&mdss0_dp3_in>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + mdss0_intf6_out: endpoint { > + remote-endpoint = <&mdss0_dp2_in>; > + }; > + }; > + }; > + > + mdss0_mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + just curious, where are mdss0_dp0 and mdss0_dp1?. Are two dp/usb combo phys not going used? > + mdss0_dp2: displayport-controller@ae9a000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0xae9a000 0 0x200>, > + <0 0xae9a200 0 0x200>, > + <0 0xae9a400 0 0x600>, > + <0 0xae9b000 0 0x400>; > + interrupt-parent = <&mdss0>; > + interrupts = <14>; > + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, > + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; > + > + phys = <&mdss0_dp2_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss0_dp2_opp_table>; > + power-domains = <&rpmhpd SC8280XP_CX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss0_dp2_in: endpoint { > + remote-endpoint = <&mdss0_intf6_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss0_dp2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss0_dp3: displayport-controller@aea0000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0xaea0000 0 0x200>, > + <0 0xaea0200 0 0x200>, > + <0 0xaea0400 0 0x600>, > + <0 0xaea1000 0 0x400>; > + interrupt-parent = <&mdss0>; > + interrupts = <15>; > + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, > + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, > + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; > + > + phys = <&mdss0_dp3_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss0_dp3_opp_table>; > + power-domains = <&dispcc0 MDSS_GDSC>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss0_dp3_in: endpoint { > + remote-endpoint = <&mdss0_intf5_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss0_dp3_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + }; > + > + mdss0_dp2_phy: phy@aec2a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x0aec2a00 0 0x19c>, > + <0 0x0aec2200 0 0xec>, > + <0 0x0aec2600 0 0xec>, > + <0 0x0aec2000 0 0x1c8>; > + > + clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss0_dp3_phy: phy@aec5a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x0aec5a00 0 0x19c>, > + <0 0x0aec5200 0 0xec>, > + <0 0x0aec5600 0 0xec>, > + <0 0x0aec5000 0 0x1c8>; > + > + clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + dispcc0: clock-controller@af00000 { > + compatible = "qcom,sc8280xp-dispcc0"; > + reg = <0 0x0af00000 0 0x20000>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&mdss0_dp2_phy 0>, > + <&mdss0_dp2_phy 1>, > + <&mdss0_dp3_phy 0>, > + <&mdss0_dp3_phy 1>, > + <0>, > + <0>, > + <0>, > + <0>; > + power-domains = <&rpmhpd SC8280XP_MMCX>; > + required-opps = <&rpmhpd_opp_nom>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + status = "disabled"; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; > @@ -1972,6 +2331,485 @@ IPCC_MPROC_SIGNAL_GLINK_QMP > qcom,remote-pid = <12>; > }; > }; > + > + mdss1: display-subsystem@22000000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x22000000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc1 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1800 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss1_mdp: display-controller@22001000 { > + compatible = "qcom,sc8280xp-dpu"; > + reg = <0 0x22001000 0 0x8f000>, > + <0 0x220b0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc1 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc1 DISP_CC_MDSS_MDP_CLK>, > + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <460000000>, > + <19200000>; > + > + operating-points-v2 = <&mdss1_mdp_opp_table>; > + power-domains = <&rpmhpd SC8280XP_MMCX>; > + > + interrupt-parent = <&mdss1>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss1_intf0_out: endpoint { > + remote-endpoint = <&mdss1_dp0_in>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + mdss1_intf4_out: endpoint { > + remote-endpoint = <&mdss1_dp1_in>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + mdss1_intf5_out: endpoint { > + remote-endpoint = <&mdss1_dp3_in>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + mdss1_intf6_out: endpoint { > + remote-endpoint = <&mdss1_dp2_in>; > + }; > + }; > + }; > + > + mdss1_mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > + mdss1_dp0: displayport-controller@22090000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0x22090000 0 0x200>, > + <0 0x22090200 0 0x200>, > + <0 0x22090400 0 0x600>, > + <0 0x22091000 0 0x400>; > + interrupt-parent = <&mdss1>; > + interrupts = <12>; > + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; > + > + phys = <&mdss1_dp0_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss1_dp0_opp_table>; > + power-domains = <&rpmhpd SC8280XP_CX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss1_dp0_in: endpoint { > + remote-endpoint = <&mdss1_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss1_dp0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > + }; > + > + mdss1_dp1: displayport-controller@22098000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0x22098000 0 0x200>, > + <0 0x22098200 0 0x200>, > + <0 0x22098400 0 0x600>, > + <0 0x22099000 0 0x400>; > + interrupt-parent = <&mdss1>; > + interrupts = <13>; > + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, > + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; > + > + phys = <&mdss1_dp1_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss1_dp1_opp_table>; > + power-domains = <&rpmhpd SC8280XP_CX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss1_dp1_in: endpoint { > + remote-endpoint = <&mdss1_intf4_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss1_dp1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss1_dp2: displayport-controller@2209a000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0x2209a000 0 0x200>, > + <0 0x2209a200 0 0x200>, > + <0 0x2209a400 0 0x600>, > + <0 0x2209b000 0 0x400>; > + interrupt-parent = <&mdss1>; > + interrupts = <14>; > + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, > + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; > + > + phys = <&mdss1_dp2_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss1_dp2_opp_table>; > + power-domains = <&rpmhpd SC8280XP_CX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss1_dp2_in: endpoint { > + remote-endpoint = <&mdss1_intf6_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss1_dp2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss1_dp3: displayport-controller@220a0000 { > + compatible = "qcom,sc8280xp-dp"; > + reg = <0 0x220a0000 0 0x200>, > + <0 0x220a0200 0 0x200>, > + <0 0x220a0400 0 0x600>, > + <0 0x220a1000 0 0x400>; > + interrupt-parent = <&mdss1>; > + interrupts = <15>; > + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, > + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, > + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; > + > + phys = <&mdss1_dp3_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&mdss1_dp3_opp_table>; > + power-domains = <&rpmhpd SC8280XP_CX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss1_dp3_in: endpoint { > + remote-endpoint = <&mdss1_intf5_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + }; > + }; > + > + mdss1_dp3_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + }; > + > + mdss1_dp2_phy: phy@220c2a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x220c2a00 0 0x19c>, > + <0 0x220c2200 0 0xec>, > + <0 0x220c2600 0 0xec>, > + <0 0x220c2000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss1_dp3_phy: phy@220c5a00 { > + compatible = "qcom,sc8280xp-dp-phy"; > + reg = <0 0x220c5a00 0 0x19c>, > + <0 0x220c5200 0 0xec>, > + <0 0x220c5600 0 0xec>, > + <0 0x220c5000 0 0x1c8>; > + > + clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", "cfg_ahb"; > + > + power-domains = <&rpmhpd SC8280XP_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + dispcc1: clock-controller@22100000 { > + compatible = "qcom,sc8280xp-dispcc1"; > + reg = <0 0x22100000 0 0x20000>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <0>, > + <&mdss1_dp0_phy 0>, > + <&mdss1_dp0_phy 1>, > + <&mdss1_dp1_phy 0>, > + <&mdss1_dp1_phy 1>, > + <&mdss1_dp2_phy 0>, > + <&mdss1_dp2_phy 1>, > + <&mdss1_dp3_phy 0>, > + <&mdss1_dp3_phy 1>, > + <0>, > + <0>, > + <0>, > + <0>; > + power-domains = <&rpmhpd SC8280XP_MMCX>; > + required-opps = <&rpmhpd_opp_nom>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + status = "disabled"; > + }; > }; > > thermal-zones {
On Fri, Nov 18, 2022 at 03:15:25PM -0800, Kuogee Hsieh wrote: > > On 10/25/2022 8:26 PM, Bjorn Andersson wrote: [..] > > + mdss0: display-subsystem@ae00000 { [..] > > + > just curious, where are mdss0_dp0 and mdss0_dp1?. Are two dp/usb combo phys > not going used? They are, but at the time of posting this, the QMP nodes was still being reworked to support expressing the DP-part of things. Now that the rework is in place I will include them as I respin this series. Regards, Bjorn